214
Junior Member level 2
I want to follow this algorithm :
d=output(2n+1)-(1/2)[output(2n)+output(2n+2)]
where ''output'' is an array consisting of 64 values...
after each clock cycle ''d'' gets a definite value based on calculation
so according to this algorithm d must contain 31 values...
but this algorithm should start once all the values are loaded in output...(that means i have to create a delay and then only the above algorithm should start working)
my code is
---main code
entity test is
architecture arch of test is
---testbench
architecture bench of test_tb is
but my ''d'' is showing garbage values
d=output(2n+1)-(1/2)[output(2n)+output(2n+2)]
where ''output'' is an array consisting of 64 values...
after each clock cycle ''d'' gets a definite value based on calculation
so according to this algorithm d must contain 31 values...
but this algorithm should start once all the values are loaded in output...(that means i have to create a delay and then only the above algorithm should start working)
my code is
---main code
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 package newtype is type row_t is array(0 to 63) of integer; type approx_t is array(0 to 30) of integer; type matrix_t is array(0 to 7, 0 to 7) of integer; end newtype; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; use work.newtype.all;
entity test is
Code VHDL - [expand] 1 2 3 4 5 port(input: in matrix_t; clk: in std_logic; output : inout row_t; d : out approx_t); end test;
architecture arch of test is
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 signal matrix : matrix_t; signal temp_row : integer; signal temp_approx : integer; signal i : unsigned(5 downto 0) := "000000"; signal n : unsigned(4 downto 0) := "00000"; signal count : unsigned(6 downto 0) := "0000000"; signal limit : unsigned (6 downto 0) := "1111111"; signal row, col : unsigned(2 downto 0) := "000"; begin process(clk) begin if rising_edge(clk) then temp_row <= input(to_integer(row), to_integer(col)); output(to_integer(i)) <=temp_row; col <= col + 1; if col = "111" then row <= row + 1; end if; i<=i+1; count <= count + 1; if count >= limit then temp_approx <= output(2*((to_integer(n)))+1)-(1/2)*(output(2*((to_integer(n))))+output(2*((to_integer(n)))+2)); d(to_integer(n)) <= temp_approx; n<= n+1; end if; end if; end process; end arch;
---testbench
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 library IEEE; use IEEE.Std_logic_1164.all; use ieee.std_logic_unsigned.all; use IEEE.Numeric_Std.all; use work.newtype.all; entity test_tb is end;
architecture bench of test_tb is
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 component test port(input: in matrix_t; clk: in std_logic; output : inout row_t; d : out approx_t); end component; signal input: matrix_t; signal clk: std_logic; signal output: row_t; signal d: approx_t; constant clock_period: time := 0.1ns; signal stop_the_clock: boolean; begin uut: test port map ( input => input, clk => clk , output => output); stimulus: process begin input <= ((0,1,2,9,10,5,8,4), (3,5,6,10,2,9,10,5), (9,8,11,2,10,2,9,10), (9,7,1,6,10,2,9,10),(1,4,5,3,6,10,8,9),(14,2,3,5,6,7,8,9),(9,7,1,6,10,2,9,10),(12,4,7,8,9,2,12,0)); wait for 50ns; stop_the_clock <= true; wait; end process; clocking: process begin while not stop_the_clock loop clk <= '1', '0' after clock_period/2; wait for clock_period; end loop; wait; end process; end;
but my ''d'' is showing garbage values
Last edited by a moderator: