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| component test
port(input: in matrix_t;
clk: in std_logic;
output : inout row_t;
d : out approx_t);
end component;
signal input: matrix_t;
signal clk: std_logic;
signal output: row_t;
signal d: approx_t;
constant clock_period: time := 0.1ns;
signal stop_the_clock: boolean;
begin
uut: test port map ( input => input,
clk => clk ,
output => output);
stimulus: process
begin
input <= ((0,1,2,9,10,5,8,4), (3,5,6,10,2,9,10,5), (9,8,11,2,10,2,9,10), (9,7,1,6,10,2,9,10),(1,4,5,3,6,10,8,9),(14,2,3,5,6,7,8,9),(9,7,1,6,10,2,9,10),(12,4,7,8,9,2,12,0));
wait for 50ns;
stop_the_clock <= true;
wait;
end process;
clocking: process
begin
while not stop_the_clock loop
clk <= '1', '0' after clock_period/2;
wait for clock_period;
end loop;
wait;
end process;
end; |