torlies
Newbie level 4
We are now going to re-build a new package and PCB of one old chip.
The package design house need us to give out a detailed constraints on some aspects such as impedance, longest wire(or worst delay), insertion loss/return loss, time skew in group, etc. I dont know how to finish some of them as none in our lab did that before.
Can anyone told me how to give out these constraints?
Especially, the PC133 DRAM controller module is important in this problem. Can anybody give me an example of how to give constraints of it?
The package design house need us to give out a detailed constraints on some aspects such as impedance, longest wire(or worst delay), insertion loss/return loss, time skew in group, etc. I dont know how to finish some of them as none in our lab did that before.
Can anyone told me how to give out these constraints?
Especially, the PC133 DRAM controller module is important in this problem. Can anybody give me an example of how to give constraints of it?