how to get pin width from other module in verilog verify?

i'm developing a function coverage for an exist design module module_m. some input of module_m is defined by parameters. my function coverage should also use the parameters to define the input port. so, the problem is: how can i get the right value from the design file and pass it to my m_fcoverage.sv file?
the limit is i can't modify the rtl design file. i can only new a m_fcoverage.sv to realized it. how can i do?

//module module_m in module_m.v
module module_m(A,B,C);

parameter A_WIDTH = 32;

input [A_WIDTH-1 : 0] A;
input B;
output C;

...
endmodule

//module top.v
module top(...);

module_m #(.A_WIDTH(16)) u_m(.A(a),.B(b),.C(c));
...
endmodule

//my new file for function coverage
module m_fcoverage(A,B,C);

parameter WHATWIDTH= 8;
input [WHATWIDTH-1 : 0] A;
input B;
input C;

covergroup cg @(B)
...
endgroup

cg cg=new();
endmodule

bind module_m m_fcovrage #(.WHATWIDTH(WHATWIDTH)) m_fcovrage(A,B,C);


then how can i get the correct value for WHATWIDTH?