How to get FMAX from vivado

[BartlebyScrivener]

I have synthesized and implemented a design by pressing the run implementation button in vivado, all I want is to know what frequency the design can run at but can't seem to find it?

Thanks

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Ok, I found timing reports and I think the reason I can't see an FMAX is I am synthesizing to small a part of my design.

 

[BartlebyScrivener]

I have now re-written my design so that it has registered inputs and outputs, but I still can't find a frequency anywhere?

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I am getting an implementation error, 'no user defined clocks found in the design'. Does it not just work that out itself?

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I have now constrained a clock, and I am getting some results but I still can't find FMAX.

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Ok, it seems vivado doesn't provide FMAX, you have to constrain it, then see if it passes, and repeat until it fails. At this point you examine the worst path failure. No idea why it doesn't.

 

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I have now re-written my design so that it has registered inputs and outputs, but I still can't find a frequency anywhere?
I am getting an implementation error, 'no user defined clocks found in the design'. Does it not just work that out itself?
I have now constrained a clock, and I am getting some results but I still can't find FMAX.

You do know that the inverse of the longest setup time will be your Fmax as that is the worst case path.

Ok, it seems vivado doesn't provide FMAX, you have to constrain it, then see if it passes, and repeat until it fails. At this point you examine the worst path failure. No idea why it doesn't.

Well it doesn't do what you want (student?), because it does what working engineers want it to do. A working engineer will say: I've designed the logic to run at 400MHz now I want the tools to place and route the design so it runs at 400MHz. If the tools don't meet timing and the engineer heavily pipelined the design then said engineer will switch to Altera.

Personally I could care less what the absolute best case Fmax of my designs might be. What I want is the tools to meet my required clock frequency, because that is what I need for my design to function in the system.

Regards