you can find answer in almost every textbook. normally you need to generate nonoverlapping logic first, by delaying the original clock and then pass it through NAND gate with the original signal. or more complicated one.
then you may estimate the load of control logic, and scale the output buffer.
CLK and CLKB to drive a RS trgger, then the RS trigger will give an overlap clock. Inverse the overlap clock you can get non-overlap. You can add buffers in RS trigger's loop to control the non-overlap time.
I think for most application SC circuits use these simple 2 phase ck gen is ok. What's your application???
I've just finished one clock circuit to generate 4 phase non-overlap for SC. However I have no good idea too and just use 2X clock rate and tranditional 2 non-overlap phase clock generator to fulfill the job.
Sorry, I don't know how to post a picture.
To be simplified. It have a 2X clock rate input, so when you followed it with a tranditional 2 non-overlap phase generator, it will output non-overlap clock pulse width is the <1/4 of 1X clock cycle. Then, use 1X clock (just halfed the input frequency) as an enable signal to switch between PH1/2 and PH3/4.
Do you mean reference paper or data? This is only a temporary solution which comes from the conventional 2-phase clock gen and requires 2X clock on system level. So no reference for such type and may have certain risk ( the 4 phase need to be aligned with the 1X clock).