How to generate ns programmable delay

[invexed]

Hi There !!

I'm trying to use the CoolRunner-II CPLD XC2C256 propagation delay to create adjustable delays of several ns duration. I can not use FPGA because the cost is too high compared with a CPLD

Such delays are typically used in physical experiments to detect the arrival of 2 events within a specified time window.
I'm sure it's possible to do this kind of delays because there are systems built with CPLD programmable time windows

My first idea is to generate a programmable pulse of constant duration

Regardless of the input pulse duration, the output pulse duration will always have a programmable delay created by a multiplexer like this:




Although the accuracy of the window using the propagation delay is not very large, it is possible to obtain acceptable results.

Although I managed to generate delays of several ns, programming in Verilog
this programm is not translated exactly as the desired circuit because optimization synthesizer XILINX

For instance
By placing several inverters connected in series, the synthesizer optimizes this elements and removes all inverters

Can I disable the optimization of the synthesizer?

Is there any way to implement this circuit in a CPLD XC2C256?


Best Regards

 

[FvM]

I can't tell how this works with Xilinx tools, but you'll need vendor specific synthesis attributes and possibly global synthesis options. With Altera Quartus, a synthesis keep attribute for respective nets and for CPLD a global setting IGNORE_LCELL_BUFFERS OFF do the trick.