In your memory(FIFO) if the read address and write address are equal then the FIFO is empty"wr_add[n:0]==rd_add[n:0]" and where as in Full case, you should ~the MSB of write address and then compare the wr_add and rd_add if both are equal then you can say FIFO is full else FIFO is not full.."{~wr_add[n],wr_add[n-1:0]} == rd_add[n:0]"
In your memory(FIFO) if the read address and write address are equal then the FIFO is empty"wr_add[n:0]==rd_add[n:0]" and where as in Full case, you should ~the MSB of write address and then compare the wr_add and rd_add if both are equal then you can say FIFO is full else FIFO is not full.."{~wr_add[n],wr_add[n-1:0]} == rd_add[n:0]"
then you need to define a variable pointer_difference, compare the both wr_add_ptr and rd_add_ptr and store the difference in pointer_difference so that you can estimate weather FIFO is almost_full or almost_empty.
go through this link you may gain more knowledge about FIFO..
then you need to define a variable pointer_difference, compare the both wr_add_ptr and rd_add_ptr and store the difference in pointer_difference so that you can estimate weather FIFO is almost_full or almost_empty.
go through this link you may gain more knowledge about FIFO..
always @(*) //pointer difference is evaluated for both clock edges
begin
if(w_ptr>r_ptr)
ptr_diff<=w_ptr-r_ptr;
else if(w_ptr)
ptr_diff<=((f_depth-r_ptr)+w_ptr);
else ptr_diff<=0; end
you can't compare two counters with gates, when the two counters are running on different clocks. The results from the comparison will not always be stable on any given clock edge, due to possible recent count on the edge of the other clock.