module clk_div5(
// Outputs
clko,
// Inputs
clk, reset_n
);
input clk, reset_n;
output clko;
reg [2:0] count_p, count_n;
assign clko = count_n[1] | count_p[1];
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
count_p <= 0;
end else begin
count_p <= (count_p == 4)? 0 : count_p + 1;
end
end
always @(negedge clk or negedge reset_n) begin
if (!reset_n) begin
count_n <= 0;
end else begin
count_n <= (count_n == 4)? 0 : count_n + 1;
end
end
endmodule // clk_div5