How to generate a pattern for generating divide by 5 clk ?

[alam.tauqueer]

Hi ,

Can any one tell me how to design a FSM for designing a circuit which give us divide by 5 clk.

I want to like how to generate a pattern for generating divide by 5 clk.

It is a interview question and its very important ....

I will be thankful for help.

Regards,
Tauqueer

 

[Lord Banshee]

design a state machine to divide the clock by 5

I had a similar question last semester

The thing was is just like your question, they did not say it has to be a 50% duty cycle. So all you do is have a five state FSM. Which is high for one state out of the the 5.

so
_--_--_--_--_--

turns to this
__________---


Well i hope this is right

 

[robinh]

Re: divide by 5 clock

The last response is right.

You can see it another way : imagine you have a counter by 5 (0 to 4). This defines 5 cycles. The clock is generated by testing the output of the counter.
From 0 to 3 the output would be 0. For the fith value (4), the output would be 1.
This is an easy way to build a divide by 5 clock. It corrsponds to a structural view of a Mealy machine. If you like, you can synchronize the divided clock with the original clock, by adding a D-flipflop on the output.

 

[alam.tauqueer]

divide by 5 clock

BUT HOW TO GENERATE A 50% DUTY CYCLE ...

Please tell me how to get this?

Regards,
Tauqueer

 

[FvM]

Re: divide by 5 clock

That's impossible in a fully synchronous design, but could be achieved by combining the input clock combinationally with the counter respectively "FSM" output. You have to take care not to generate glitches this way, so it's surely not recommended design practice. But it may be useful in some cases anyway.

 

[j_andr]

Re: divide by 5 clock

BUT HOW TO GENERATE A 50% DUTY CYCLE

try such solution, not exactly 50/50, but close to;

module div_by_5
(
   input        clk,
   output  reg  clk_div
);

reg  [5:1] set = 5'h01;
reg        clr;

always @(posedge clk)
  begin
   set[1] <= set[5];
   set[2] <= set[1];
   set[3] <= set[2];
   set[4] <= set[3];
   set[5] <= set[4];
  end 

always @(negedge clk)
    clr <= set[3];

always @(posedge set[1] or posedge clr)
   if ( clr)   clk_div <= 1'b0;
   else        clk_div <= 1'b1;
endmodule

the trick is to use negedge;

J.A

 

[balan]

Re: divide by 5 clock

hi,
check out this website www.onsemi.com

 

[nand_gates]

Re: divide by 5 clock

Checkout this one!

module clk_div5(
   // Outputs
   clko, 
   // Inputs
   clk, reset_n
   );
   input clk, reset_n;
   output      clko;
   reg [2:0]   count_p, count_n;
   assign      clko = count_n[1] | count_p[1];
   
   always @(posedge clk or negedge reset_n) begin
      if (!reset_n) begin
         count_p <= 0;
      end else begin
         count_p <= (count_p == 4)? 0 : count_p + 1;
      end
   end
   
   always @(negedge clk or negedge reset_n) begin
      if (!reset_n) begin
         count_n <= 0;
      end else begin
         count_n <= (count_n == 4)? 0 : count_n + 1;
      end
   end
endmodule // clk_div5

 

[Zerox100]

Re: divide by 5 clock

Hi,
I have a cool solution. You can use a divide by 2.5 and then a divide by 2 and you will have a divide by 5. Purely 50-50. I have posted the code of divide by 2.5 but i repost it here!


--////////////////////////////////////////
library IEEE;
use ieee.std_logic_1164.all;

entity divide2_5 is
port (
clk : in std_logic ;
reset : in std_logic ;
div : out std_logic
);
end divide2_5;

architecture st of divide2_5 is
signal d, q, p : std_logic_vector (1 downto 0);
signal fb : std_logic;

begin

process (clk, reset)
begin
if (reset = '0') then
q(0) <= '0';
elsif (clk'event and clk = '1') then
q(0) <= p(0);
end if;
end process;

process (clk, reset)
begin
if (reset = '0') then
p(0) <= '0';
elsif (clk'event and clk = '1') then
p(0) <= d(0);
end if;
end process;

process (clk, reset)
begin
if (reset = '0') then
q(1) <= '0';
elsif (clk'event and clk = '0') then
q(1) <= p(1);
end if;
end process;

process (clk, reset)
begin
if (reset = '0') then
p(1) <= '0';
elsif (clk'event and clk = '0') then
p(1) <= d(1);
end if;
end process;

fb <= NOT(q(0) OR q(1) or p(1) OR P(0));
d(0)<= fb;
d(1)<= fb;
--div <= fb; --20%
div <= p(0) or p(1); --40%

end st;
--///////////////////////////////////////

 

[echo47]

divide by 5 clock

Dividing by 2.5 then by 2 still won't guarantee 50% output duty cycle.
In all purely digital solutions, the output duty cycle varies with the symmetry of the input clock.

 

[muralicrl]

Re: divide by 5 clock

Hi,

It is very simple to generate divide by 5, You can have two state machine processes, One with two rising edge clocks and other with falling edge clocks. Then finally and them that's all.

 

[alam.tauqueer]

divide by 5 clock

Hi Murali,

can u please explain it little bit more.

Regards,
Tauqueer

 

[mmarco76]

divide by 5 clock

Wanna a reliable way?
Use the PLL on the device and you'll be ok.

Really the question is not usefull imo because in digital environment you don't need 50% DC and if you need it it's for something of analog outside the FPGA so use PLL will make you do the DC you wanna and also move your CLK_OUT in time.

If it's a pure "code" problem the suggestions that has been given are all correct.

 

[satish_mahankali]

Re: divide by 5 clock

U can achive div 5 with 50 % duty cycle.
Instead of looking designing dirctly in HDL pls do try to analyse the design

means draw a clk sequence

then take the o/p what u want from that start analysing the ckt them\n u can...

 

[Yuphone]

Re: divide by 5 clock

module div_by_5 (
  input   i_clk,
  input   rst_n,
  output  o_clk
);
 
parameter N = 5; 
      
reg [3:0] cnt_p;
reg [3:0] cnt_n;
 
reg clk_p;
reg clk_n;
 
assign o_clk = clk_n & clk_p;

always @ (posedge i_clk or negedge rst_n)
begin
  if (!rst_n)
    cnt_p <= 0;
  else
  begin
    if (cnt_p == N-1)
      cnt_p <= 0;
    else
      cnt_p <= cnt_p + 1;
  end
end

// 0~(N>>1) ↑ -> 1; ((N>>1)+1)~(N-1) ↑ -> 0
always @ (posedge i_clk or negedge rst_n)
begin
  if (!rst_n)
    clk_p <= 0;
  else
  begin
    if (cnt_p <= (N>>1)) // 0 ~ (N>>1)
      clk_p <= 1;
    else 
      clk_p <= 0;
  end
end


always @ (negedge i_clk or negedge rst_n)
begin
  if (!rst_n)
    cnt_n <= 0;
  else
  begin
    if (cnt_n == N-1)
      cnt_n <= 0;
    else
      cnt_n <= cnt_n + 1;
  end
end

// 0~(N>>1) ↓ -> 1; ((N>>1)+1)~(N-1) ↓ -> 0
always @ (negedge i_clk or negedge rst_n)
begin
  if (!rst_n)
    clk_n <= 0;
  else
  begin
    if (cnt_n <= (N>>1)) // 0 ~ (N>>1)
      clk_n <= 1;
    else 
      clk_n <= 0;
  end
end
 
endmodule