Re: VHDL to LAYOUT
Hi Vivek,
As GLISS has mentioned about h**p://www-asim.lip6.fr/recherche/alliance/
Alliance is the one of the free available tools that can generate layout from VHDL,
and This is absolutely free, u have versions that can be worked in both windows and linux environment,
But the restriction in that tool, it can't support all the features of VHDL,
U go through the tool website,
it supports only datamodel of VHDL and NOT the BEHAVIOURAL of VHDL,
so it will be quite challeging task for you for generating the VHDL code that is fully supported in the alliance,
As per your requirment, that u have to do power analysis and delay analysis,
i think u have to go for some STANDARD ASIC tools from SYNOPSYS or CADENCE or MENTOR or MAGMA,
no other tools is there to give u very good analysis regarding power and timing