vivek_raj_verma
Junior Member level 2
hi all,
I Have implemented a fast multiplier architecture in Xilinx using VHDL. I want to generate layout for correspoding architecture and do some power and delay analysis.
So how can i do that?? I have Tanner tool (T spice, S edit and L edit ) in my lab. So is tanner provides some tool that can generate the layout from VHDL code or if there is any other tool i can use. If there is some other tool, can i download it for free.
Any help will be good to me.
vivek
I Have implemented a fast multiplier architecture in Xilinx using VHDL. I want to generate layout for correspoding architecture and do some power and delay analysis.
So how can i do that?? I have Tanner tool (T spice, S edit and L edit ) in my lab. So is tanner provides some tool that can generate the layout from VHDL code or if there is any other tool i can use. If there is some other tool, can i download it for free.
Any help will be good to me.
vivek