How to generate a layout from architecture implemented using VHDL?

[vivek_raj_verma]

hi all,

I Have implemented a fast multiplier architecture in Xilinx using VHDL. I want to generate layout for correspoding architecture and do some power and delay analysis.

So how can i do that?? I have Tanner tool (T spice, S edit and L edit ) in my lab. So is tanner provides some tool that can generate the layout from VHDL code or if there is any other tool i can use. If there is some other tool, can i download it for free.

Any help will be good to me.

vivek

 

[vivek_raj_verma]

register from vhdl to layout

Hi,

Can anyone give me some idea????

 

[gliss]

Re: VHDL to LAYOUT

Hi,
Try Alliance:
http://www-asim.lip6.fr/recherche/alliance/

 

[vivek_raj_verma]

VHDL to LAYOUT

Hi Gliss,
thanks.

But i want to know whether this site gives us the free tools to do our work(if i m getting the tool which serves my purpose).

Can u tell me in detail if u know more????

Can it really offers some tool which can convert the vhdl code to a netlist which can generate layout.


thks again.

vivek

 

[vivek_raj_verma]

VHDL to LAYOUT

Hi there,
Is there anyone more who can help me on this ?????
vivek

 

[anjali]

Re: VHDL to LAYOUT

hi vivek, usign ISE tool you can do place & route for implementation in FPGA.
but i dont know whether its a free tool or not.

they might be giving some trail version of the tools. just try.

 

[Ahmed Ragab]

Re: VHDL to LAYOUT

Yes the Xilinx ISE webpack is for free all you need to do is to register yourself on their site and then you may download it all.

I don't know to what extent it may help you, but some of my friends mentioned that at some point the webpack ISE wasn't useful and they needed the Foundation version of it "needs money".

Try checking some p2p programs to find what you want.
and pm me if you need anything.

Salam.

 

[au_sun]

Re: VHDL to LAYOUT

Hi Vivek,

As GLISS has mentioned about h**p://www-asim.lip6.fr/recherche/alliance/

Alliance is the one of the free available tools that can generate layout from VHDL,
and This is absolutely free, u have versions that can be worked in both windows and linux environment,

But the restriction in that tool, it can't support all the features of VHDL,
U go through the tool website,
it supports only datamodel of VHDL and NOT the BEHAVIOURAL of VHDL,

so it will be quite challeging task for you for generating the VHDL code that is fully supported in the alliance,

As per your requirment, that u have to do power analysis and delay analysis,
i think u have to go for some STANDARD ASIC tools from SYNOPSYS or CADENCE or MENTOR or MAGMA,
no other tools is there to give u very good analysis regarding power and timing

 

[vivek_raj_verma]

VHDL to LAYOUT

thanks for the suggestions frnds. I have the ISE 7.1 tools in my institute lab so that is not a problem, the problem is to generate a layout as we do in cadence and t spice etc. So how that can be generated from VHDL code. There is a tool in cadence that can genrate this kiind of thng from verilog . so i m looking for any free tool like that.

thanks for the help

vivek

 

[gliss]

VHDL to LAYOUT

Maybe there isn't a free tool that has that feature
like au_sun said, I think you need a professional tool

 

[smith_kang]

Re: VHDL to LAYOUT

Hi Vivek,
I think you are confused with FPGA & ASIC. Cadence can give you RTL to GDS(Layout) but it is not a free tool.Also Cadence or Magma or PC can give you layout from VHDL also.But synthesis and handling a VHDL netlist is very tricky thats why ppl are using verilog.
HDL is not a issue in your case as you can convert VHDL to Verilog easily with free tools available on net.
What you can do is to make small module with the help of Tanner and then integrate them in top module.I think your design is not so big and you can make different modules easily.

 

[vivek_raj_verma]

VHDL to LAYOUT

thanks smith,

U r right. Cadence can give me a layout from vhdl. But i dont have that tool in the lab. so i was looking for an alternative. Also as u have said i can do in tanner too using hierarchy but surely that will consume more time. It was my minor project only so i wanted some easy way out. anyway thanks for the help.

If u have any other idea. Plz tell me.

bye for now

 

[aminpix]

Re: VHDL to LAYOUT

Which tools of cadence are used to convert VHDL to layout? I have the same problem, i mean i have to convert a VHDL to layout. I have cadence but I dont know how t use it
Is there any tutorial on internet?

 

[randyest]

Re: VHDL to LAYOUT

Which tools of cadence are used to convert VHDL to layout? I have the same problem, i mean i have to convert a VHDL to layout. I have cadence but I dont know how t use it
Is there any tutorial on internet?

SOC Encounter supports VHDL import. It's pretty similar to verilog import -- there's an import dialog box to set libraries / files etc. See the SOCE docs for details.

 

[abhi_459]

Re: VHDL to LAYOUT

write ur code in verilog..and use
microwind software for generation of layout

 

[aria62]

Hi,
you can import your VHDL code in "Synopsys Design Compiler" and create a structural netlist. Then export this netlist to "Cadence SOC encounter" to generate a layout.

regards