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How to generate 125MHz to synchronize RXD for MAC CORE?

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tavidu

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Now i am designing Mac(100M/1000M/TBI)
But I meet a problem.
When at TBI mode, RX deirection, two clocks are provided by PHY chip:
RX_CLK_TBI0 and RX_CLK_TBI1, they are both 62.5MHz.
After TBI processing, RXD, RX_DV, RX_ER are transmited to MAC CORE,
but how to generate 125MHz to synchronize RXD for MAC CORE?
 

dolby.yang

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Re: MAC IP CORE design

i think you need a external clk source.
 

visualart

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MAC IP CORE design

you may flip with the rising and falling edge from the 62.5MHz clock. It is fittable to the 125MHz.
 

ashgun

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Re: MAC IP CORE design

When you are using TBI mode in 1gbps mode , the phy provides 2 clocks of 62.5 Mhz , but as you are working in 125 Mhz clock on your mac side you will have to use that clock to synchronise the data for MAC Core
 

tutu_xie

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MAC IP CORE design

My understanding is:
All 100/1000M Mac needs a external 125M clk resource to feed internal PLL, you know when in 1GE mode, MAC also needs to send this clk to PHY
 

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