Re: setup violation
hi,
Setup violation results because the data didnot arrive setup time before the active clock edge:
so ,Let's analyse the reasons for this ,the data didnot arrive before the specified time because there has been a significant delay in data path.If you analyse the timing report you find the because of the added buffers in combi logic path,we get a delay.
These buffers are needed for increasing the drive strength of thesignal .So according to the reasons stated above ,we come to conclusion the buffers can't be removed .But you have to fix setup violation.
We have 2 options now:
1).Decresing frequency so that you give an additional cycle for data to reach ,so that there is no setup violation.But our promise of design which would run at particular frequency would fail.so we abondon the approach.
2).Going back to discussion in the 1st paragraph we need to upsize the buffer ,which would result in buffer being replace with a footprint ,with decreased delay and high drive strength .
This is how we fix setup violations.