How to fix problem in my Verilog code

lynk111 · Jun 22, 2011

I couldn't fix this, something wrong in always @, pleas help me, thank

module Lab2ex2part5(A1,A0,B1,B0,S2,S1,S0,SW,HEX0,HEX1,HEX2,HEX4,HEX5,HEX6,HEX7);
input [15:0]SW;
input [3:0]A1,A0,B1,B0;
output [3:0]S2,S1,S0;
output [6:0]HEX1,HEX0,HEX2,HEX4,HEX5,HEX6,HEX7;
wire [3:0]A1,A0,B1,B0;
reg [3:0]x,y,z;
/*display A0 = SW[7:4] on HEX6*/
assign HEX6[0]=(~SW[6]&~SW[5]&SW[4])|(~SW[7]&SW[6]&~SW[5]&~SW[4]);
assign HEX6[1]=(~SW[7]&SW[6]&~SW[5]&SW[4])|(~SW[7]&SW[6]&SW[5]&~SW[4]);
assign HEX6[2]=(~SW[7]&~SW[6]&SW[5]&~SW[4]);
assign HEX6[3]=(~SW[7]&~SW[6]&~SW[5]&SW[4])|(SW[6]&~SW[5]&~SW[4])|(SW[6]&SW[5]&SW[4]);
assign HEX6[4]=(~SW[7]&~SW[6]&~SW[5]&SW[4])|(~SW[7]&~SW[6]&SW[5]&SW[4])|(~SW[7]&SW[6]&~SW[5]&~SW[4])|(~SW[7]&SW[6]&~SW[5]&SW[4])|
(~SW[7]&SW[6]&SW[5]&SW[4])|(SW[7]&~SW[6]&~SW[5]&SW[4]);
assign HEX6[5]=(~SW[7]&~SW[6]&~SW[5]&SW[4])|(~SW[7]&~SW[6]&SW[5]&~SW[4])|(~SW[7]&~SW[6]&SW[5]&SW[4])|(~SW[7]&SW[6]&SW[5]&SW[4]);
assign HEX6[6]=(~SW[7]&~SW[6]&~SW[5]&~SW[4])|(~SW[7]&~SW[6]&~SW[5]&SW[4])|(~SW[7]&SW[6]&SW[5]&SW[4]);

/*display A1 = SW[3:0] on HEX4*/

assign HEX7[0]=(~SW[2]&~SW[1]&SW[0])|(~SW[3]&SW[2]&~SW[1]&~SW[0]);
assign HEX7[1]=(~SW[3]&SW[2]&~SW[1]&SW[0])|(~SW[3]&SW[2]&SW[1]&~SW[0]);
assign HEX7[2]=(~SW[3]&~SW[2]&SW[1]&~SW[0]);
assign HEX7[3]=(~SW[3]&~SW[2]&~SW[1]&SW[0])|(SW[2]&~SW[1]&~SW[0])|(SW[2]&SW[1]&SW[0]);
assign HEX7[4]=(~SW[3]&~SW[2]&~SW[1]&SW[0])|(~SW[3]&~SW[2]&SW[1]&SW[0])|(~SW[3]&SW[2]&~SW[1]&~SW[0])|(~SW[3]&SW[2]&~SW[1]&SW[0])|
(~SW[3]&SW[2]&SW[1]&SW[0])|(SW[3]&~SW[2]&~SW[1]&SW[0]);
assign HEX7[5]=(~SW[3]&~SW[2]&~SW[1]&SW[0])|(~SW[3]&~SW[2]&SW[1]&~SW[0])|(~SW[3]&~SW[2]&SW[1]&SW[0])|(~SW[3]&SW[2]&SW[1]&SW[0]);
assign HEX7[6]=(~SW[3]&~SW[2]&~SW[1]&~SW[0])|(~SW[3]&~SW[2]&~SW[1]&SW[0])|(~SW[3]&SW[2]&SW[1]&SW[0]);

/*display B0 = SW[7:4] on HEX6*/
assign HEX4[0]=(~SW[6]&~SW[5]&SW[4])|(~SW[7]&SW[6]&~SW[5]&~SW[4]);
assign HEX4[1]=(~SW[7]&SW[6]&~SW[5]&SW[4])|(~SW[7]&SW[6]&SW[5]&~SW[4]);
assign HEX4[2]=(~SW[7]&~SW[6]&SW[5]&~SW[4]);
assign HEX4[3]=(~SW[7]&~SW[6]&~SW[5]&SW[4])|(SW[6]&~SW[5]&~SW[4])|(SW[6]&SW[5]&SW[4]);
assign HEX4[4]=(~SW[7]&~SW[6]&~SW[5]&SW[4])|(~SW[7]&~SW[6]&SW[5]&SW[4])|(~SW[7]&SW[6]&~SW[5]&~SW[4])|(~SW[7]&SW[6]&~SW[5]&SW[4])|
(~SW[7]&SW[6]&SW[5]&SW[4])|(SW[7]&~SW[6]&~SW[5]&SW[4]);
assign HEX4[5]=(~SW[7]&~SW[6]&~SW[5]&SW[4])|(~SW[7]&~SW[6]&SW[5]&~SW[4])|(~SW[7]&~SW[6]&SW[5]&SW[4])|(~SW[7]&SW[6]&SW[5]&SW[4]);
assign HEX4[6]=(~SW[7]&~SW[6]&~SW[5]&~SW[4])|(~SW[7]&~SW[6]&~SW[5]&SW[4])|(~SW[7]&SW[6]&SW[5]&SW[4]);

/*display B1 = SW[3:0] on HEX4*/

assign HEX5[0]=(~SW[2]&~SW[1]&SW[0])|(~SW[3]&SW[2]&~SW[1]&~SW[0]);
assign HEX5[1]=(~SW[3]&SW[2]&~SW[1]&SW[0])|(~SW[3]&SW[2]&SW[1]&~SW[0]);
assign HEX5[2]=(~SW[3]&~SW[2]&SW[1]&~SW[0]);
assign HEX5[3]=(~SW[3]&~SW[2]&~SW[1]&SW[0])|(SW[2]&~SW[1]&~SW[0])|(SW[2]&SW[1]&SW[0]);
assign HEX5[4]=(~SW[3]&~SW[2]&~SW[1]&SW[0])|(~SW[3]&~SW[2]&SW[1]&SW[0])|(~SW[3]&SW[2]&~SW[1]&~SW[0])|(~SW[3]&SW[2]&~SW[1]&SW[0])|
(~SW[3]&SW[2]&SW[1]&SW[0])|(SW[3]&~SW[2]&~SW[1]&SW[0]);
assign HEX5[5]=(~SW[3]&~SW[2]&~SW[1]&SW[0])|(~SW[3]&~SW[2]&SW[1]&~SW[0])|(~SW[3]&~SW[2]&SW[1]&SW[0])|(~SW[3]&SW[2]&SW[1]&SW[0]);
assign HEX5[6]=(~SW[3]&~SW[2]&~SW[1]&~SW[0])|(~SW[3]&~SW[2]&~SW[1]&SW[0])|(~SW[3]&SW[2]&SW[1]&SW[0]);

always @ *
begin
assign S0 = A0 + B0;
begin
if (S0<10)
begin
always @ (S0[3:0])
begin
case (S0[3:0])
4'b0000: begin
HEX0[0] = 0;
HEX0[1] = 0;
HEX0[2] = 0;
HEX0[3] = 0;
HEX0[4] = 0;
HEX0[5] = 0;
HEX0[6] = 1;
end
4'b0001: begin
HEX0[0] = 1;
HEX0[1] = 0;
HEX0[2] = 0;
HEX0[3] = 1;
HEX0[4] = 1;
HEX0[5] = 1;
HEX0[6] = 1;
end
4'b0010: begin
HEX0[0] = 0;
HEX0[1] = 0;
HEX0[2] = 1;
HEX0[3] = 0;
HEX0[4] = 0;
HEX0[5] = 1;
HEX0[6] = 0;
end
4'b0011: begin
HEX0[0] = 0;
HEX0[1] = 0;
HEX0[2] = 0;
HEX0[3] = 0;
HEX0[4] = 1;
HEX0[5] = 1;
HEX0[6] = 0;

end
4'b0100: begin
HEX0[0] = 1;
HEX0[1] = 0;
HEX0[2] = 0;
HEX0[3] = 1;
HEX0[4] = 1;
HEX0[5] = 0;
HEX0[6] = 0;
end
4'b0101: begin
HEX0[0] = 1;
HEX0[1] = 0;
HEX0[2] = 0;
HEX0[3] = 0;
HEX0[4] = 1;
HEX0[5] = 0;
HEX0[6] = 0;
end
4'b0110: begin
HEX0[0] = 0;
HEX0[1] = 1;
HEX0[2] = 0;
HEX0[3] = 0;
HEX0[4] = 0;
HEX0[5] = 0;
HEX0[6] = 0;
end
4'b0111: begin
HEX0[0] = 1;
HEX0[1] = 1;
HEX0[2] = 1;
HEX0[3] = 1;
HEX0[4] = 0;
HEX0[5] = 0;
HEX0[6] = 0;
end
4'b1000: begin
HEX0[0] = 0;
HEX0[1] = 0;
HEX0[2] = 0;
HEX0[3] = 0;
HEX0[4] = 0;
HEX0[5] = 0;
HEX0[6] = 0;
end
4'b1001: begin
HEX0[0] = 0;
HEX0[1] = 0;
HEX0[2] = 0;
HEX0[3] = 0;
HEX0[4] = 1;
HEX0[5] = 0;
HEX0[6] = 0;
end
endcase

HEX1[0] = 0;
HEX1[1] = 0;
HEX1[2] = 0;
HEX1[3] = 0;
HEX1[4] = 0;
HEX1[5] = 0;
HEX1[6] = 1;

HEX2[0] = 0;
HEX2[1] = 0;
HEX2[2] = 0;
HEX2[3] = 0;
HEX2[4] = 0;
HEX2[5] = 0;
HEX2[6] = 1;

end
end
else if (S1<10)
begin
x = S0 - 10;
always @ (x[3:0])
begin
case (x[3:0])
4'b0000: begin
HEX0[0] = 0;
HEX0[1] = 0;
HEX0[2] = 0;
HEX0[3] = 0;
HEX0[4] = 0;
HEX0[5] = 0;
HEX0[6] = 1;
end
4'b0001: begin
HEX0[0] = 1;
HEX0[1] = 0;
HEX0[2] = 0;
HEX0[3] = 1;
HEX0[4] = 1;
HEX0[5] = 1;
HEX0[6] = 1;
end
4'b0010: begin
HEX0[0] = 0;
HEX0[1] = 0;
HEX0[2] = 1;
HEX0[3] = 0;
HEX0[4] = 0;
HEX0[5] = 1;
HEX0[6] = 0;
end
4'b0011: begin
HEX0[0] = 0;
HEX0[1] = 0;
HEX0[2] = 0;
HEX0[3] = 0;
HEX0[4] = 1;
HEX0[5] = 1;
HEX0[6] = 0;

end
4'b0100: begin
HEX0[0] = 1;
HEX0[1] = 0;
HEX0[2] = 0;
HEX0[3] = 1;
HEX0[4] = 1;
HEX0[5] = 0;
HEX0[6] = 0;
end
4'b0101: begin
HEX0[0] = 1;
HEX0[1] = 0;
HEX0[2] = 0;
HEX0[3] = 0;
HEX0[4] = 1;
HEX0[5] = 0;
HEX0[6] = 0;
end
4'b0110: begin
HEX0[0] = 0;
HEX0[1] = 1;
HEX0[2] = 0;
HEX0[3] = 0;
HEX0[4] = 0;
HEX0[5] = 0;
HEX0[6] = 0;
end
4'b0111: begin
HEX0[0] = 1;
HEX0[1] = 1;
HEX0[2] = 1;
HEX0[3] = 1;
HEX0[4] = 0;
HEX0[5] = 0;
HEX0[6] = 0;
end
4'b1000: begin
HEX0[0] = 0;
HEX0[1] = 0;
HEX0[2] = 0;
HEX0[3] = 0;
HEX0[4] = 0;
HEX0[5] = 0;
HEX0[6] = 0;
end
4'b1001: begin
HEX0[0] = 0;
HEX0[1] = 0;
HEX0[2] = 0;
HEX0[3] = 0;
HEX0[4] = 1;
HEX0[5] = 0;
HEX0[6] = 0;
end
endcase
end

assign S1 = A1 + B1 + 1;
begin
case (S1[3:0])
4'b0000: begin
HEX1[0] = 0;
HEX1[1] = 0;
HEX1[2] = 0;
HEX1[3] = 0;
HEX1[4] = 0;
HEX1[5] = 0;
HEX1[6] = 1;
end
4'b0001: begin
HEX1[0] = 1;
HEX1[1] = 0;
HEX1[2] = 0;
HEX1[3] = 1;
HEX1[4] = 1;
HEX1[5] = 1;
HEX1[6] = 1;
end
4'b0010: begin
HEX1[0] = 0;
HEX1[1] = 0;
HEX1[2] = 1;
HEX1[3] = 0;
HEX1[4] = 0;
HEX1[5] = 1;
HEX1[6] = 0;
end
4'b0011: begin
HEX1[0] = 0;
HEX1[1] = 0;
HEX1[2] = 0;
HEX1[3] = 0;
HEX1[4] = 1;
HEX1[5] = 1;
HEX1[6] = 0;

end
4'b0100: begin
HEX1[0] = 1;
HEX1[1] = 0;
HEX1[2] = 0;
HEX1[3] = 1;
HEX1[4] = 1;
HEX1[5] = 0;
HEX1[6] = 0;
end
4'b0101: begin
HEX1[0] = 1;
HEX1[1] = 0;
HEX1[2] = 0;
HEX1[3] = 0;
HEX1[4] = 1;
HEX1[5] = 0;
HEX1[6] = 0;
end
4'b0110: begin
HEX0[0] = 0;
HEX0[1] = 1;
HEX0[2] = 0;
HEX0[3] = 0;
HEX0[4] = 0;
HEX0[5] = 0;
HEX0[6] = 0;
end
4'b0111: begin
HEX1[0] = 1;
HEX1[1] = 1;
HEX1[2] = 1;
HEX1[3] = 1;
HEX1[4] = 0;
HEX1[5] = 0;
HEX1[6] = 0;
end
4'b1000: begin
HEX1[0] = 0;
HEX1[1] = 0;
HEX1[2] = 0;
HEX1[3] = 0;
HEX1[4] = 0;
HEX1[5] = 0;
HEX1[6] = 0;
end
4'b1001: begin
HEX1[0] = 0;
HEX1[1] = 0;
HEX1[2] = 0;
HEX1[3] = 0;
HEX1[4] = 1;
HEX1[5] = 0;
HEX1[6] = 0;
end
endcase

HEX2[0] = 0;
HEX2[1] = 0;
HEX2[2] = 0;
HEX2[3] = 0;
HEX2[4] = 0;
HEX2[5] = 0;
HEX2[6] = 1;
end
end

else
begin
y = S1 -10;
always @ (y[3:0])
begin
case (y[3:0])
4'b0000: begin
HEX0[0] = 0;
HEX0[1] = 0;
HEX0[2] = 0;
HEX0[3] = 0;
HEX0[4] = 0;
HEX0[5] = 0;
HEX0[6] = 1;
end
4'b0001: begin
HEX0[0] = 1;
HEX0[1] = 0;
HEX0[2] = 0;
HEX0[3] = 1;
HEX0[4] = 1;
HEX0[5] = 1;
HEX0[6] = 1;
end
4'b0010: begin
HEX0[0] = 0;
HEX0[1] = 0;
HEX0[2] = 1;
HEX0[3] = 0;
HEX0[4] = 0;
HEX0[5] = 1;
HEX0[6] = 0;
end
4'b0011: begin
HEX0[0] = 0;
HEX0[1] = 0;
HEX0[2] = 0;
HEX0[3] = 0;
HEX0[4] = 1;
HEX0[5] = 1;
HEX0[6] = 0;

end
4'b0100: begin
HEX0[0] = 1;
HEX0[1] = 0;
HEX0[2] = 0;
HEX0[3] = 1;
HEX0[4] = 1;
HEX0[5] = 0;
HEX0[6] = 0;
end
4'b0101: begin
HEX0[0] = 1;
HEX0[1] = 0;
HEX0[2] = 0;
HEX0[3] = 0;
HEX0[4] = 1;
HEX0[5] = 0;
HEX0[6] = 0;
end
4'b0110: begin
HEX0[0] = 0;
HEX0[1] = 1;
HEX0[2] = 0;
HEX0[3] = 0;
HEX0[4] = 0;
HEX0[5] = 0;
HEX0[6] = 0;
end
4'b0111: begin
HEX0[0] = 1;
HEX0[1] = 1;
HEX0[2] = 1;
HEX0[3] = 1;
HEX0[4] = 0;
HEX0[5] = 0;
HEX0[6] = 0;
end
4'b1000: begin
HEX0[0] = 0;
HEX0[1] = 0;
HEX0[2] = 0;
HEX0[3] = 0;
HEX0[4] = 0;
HEX0[5] = 0;
HEX0[6] = 0;
end
4'b1001: begin
HEX0[0] = 0;
HEX0[1] = 0;
HEX0[2] = 0;
HEX0[3] = 0;
HEX0[4] = 1;
HEX0[5] = 0;
HEX0[6] = 0;
end
endcase
end
HEX2[0] = 1;
HEX2[1] = 0;
HEX2[2] = 0;
HEX2[3] = 1;
HEX2[4] = 1;
HEX2[5] = 1;
HEX2[6] = 1;
end
end
endmodule

lostinxlation · Jun 22, 2011

why is always nested?

thiagu_comp · Jun 22, 2011

There can not be an always statement within another always statement. In your code, there is an if stmt inside always and then again another always within that if stmt. Completely wrong way to code. Also make sure whether you want to use that procedural assign stmt inside first always.

nand_gates · Jun 23, 2011

Probably you want to add two numbers (BCD addition) and display them on 7seg displays.
Here is the code I modified to do that.. Hope this helps!

Code:

module Lab2ex2part5(A1,A0,B1,B0,S2,S1,S0,SW,HEX0,HEX1,HEX2,HEX4,HEX5,HEX6,HEX7);
   input [15:0] SW;
   input [3:0]  A1,A0,B1,B0;
   output [3:0] S2,S1,S0;
   output [6:0] HEX0, HEX1, HEX2, HEX4, HEX5, HEX6, HEX7;
   reg [3:0]    x0, x1;
   reg [3:0]    S2, S1, S0;
   reg [6:0]    HEX0, HEX1, HEX2;
   reg          cy, bcd_cy;
   
   /*display A0 = SW[7:4] on HEX6*/
   assign HEX6[0]=(~SW[6]&~SW[5]&SW[4])|(~SW[7]&SW[6]&~SW[5]&~SW[4]);
   assign HEX6[1]=(~SW[7]&SW[6]&~SW[5]&SW[4])|(~SW[7]&SW[6]&SW[5]&~SW[4]);
   assign HEX6[2]=(~SW[7]&~SW[6]&SW[5]&~SW[4]);
   assign HEX6[3]=(~SW[7]&~SW[6]&~SW[5]&SW[4])|(SW[6]&~SW[5]&~SW[4])|(SW[6]&SW[5]&SW[4]);
   assign HEX6[4]=(~SW[7]&~SW[6]&~SW[5]&SW[4])|(~SW[7]&~SW[6]&SW[5]&SW[4])|(~SW[7]&SW[6]&~SW[5]&~SW[4])|(~SW[7]&SW[6]&~SW[5]&SW[4])|
                  (~SW[7]&SW[6]&SW[5]&SW[4])|(SW[7]&~SW[6]&~SW[5]&SW[4]);
   assign HEX6[5]=(~SW[7]&~SW[6]&~SW[5]&SW[4])|(~SW[7]&~SW[6]&SW[5]&~SW[4])|(~SW[7]&~SW[6]&SW[5]&SW[4])|(~SW[7]&SW[6]&SW[5]&SW[4]);
   assign HEX6[6]=(~SW[7]&~SW[6]&~SW[5]&~SW[4])|(~SW[7]&~SW[6]&~SW[5]&SW[4])|(~SW[7]&SW[6]&SW[5]&SW[4]);
   
   /*display A1 = SW[3:0] on HEX4*/
   assign HEX7[0]=(~SW[2]&~SW[1]&SW[0])|(~SW[3]&SW[2]&~SW[1]&~SW[0]);
   assign HEX7[1]=(~SW[3]&SW[2]&~SW[1]&SW[0])|(~SW[3]&SW[2]&SW[1]&~SW[0]);
   assign HEX7[2]=(~SW[3]&~SW[2]&SW[1]&~SW[0]);
   assign HEX7[3]=(~SW[3]&~SW[2]&~SW[1]&SW[0])|(SW[2]&~SW[1]&~SW[0])|(SW[2]&SW[1]&SW[0]);
   assign HEX7[4]=(~SW[3]&~SW[2]&~SW[1]&SW[0])|(~SW[3]&~SW[2]&SW[1]&SW[0])|(~SW[3]&SW[2]&~SW[1]&~SW[0])|(~SW[3]&SW[2]&~SW[1]&SW[0])|
                  (~SW[3]&SW[2]&SW[1]&SW[0])|(SW[3]&~SW[2]&~SW[1]&SW[0]);
   assign HEX7[5]=(~SW[3]&~SW[2]&~SW[1]&SW[0])|(~SW[3]&~SW[2]&SW[1]&~SW[0])|(~SW[3]&~SW[2]&SW[1]&SW[0])|(~SW[3]&SW[2]&SW[1]&SW[0]);
   assign HEX7[6]=(~SW[3]&~SW[2]&~SW[1]&~SW[0])|(~SW[3]&~SW[2]&~SW[1]&SW[0])|(~SW[3]&SW[2]&SW[1]&SW[0]);
   
   /*display B0 = SW[7:4] on HEX6*/
   assign HEX4[0]=(~SW[6]&~SW[5]&SW[4])|(~SW[7]&SW[6]&~SW[5]&~SW[4]);
   assign HEX4[1]=(~SW[7]&SW[6]&~SW[5]&SW[4])|(~SW[7]&SW[6]&SW[5]&~SW[4]);
   assign HEX4[2]=(~SW[7]&~SW[6]&SW[5]&~SW[4]);
   assign HEX4[3]=(~SW[7]&~SW[6]&~SW[5]&SW[4])|(SW[6]&~SW[5]&~SW[4])|(SW[6]&SW[5]&SW[4]);
   assign HEX4[4]=(~SW[7]&~SW[6]&~SW[5]&SW[4])|(~SW[7]&~SW[6]&SW[5]&SW[4])|(~SW[7]&SW[6]&~SW[5]&~SW[4])|(~SW[7]&SW[6]&~SW[5]&SW[4])|
                  (~SW[7]&SW[6]&SW[5]&SW[4])|(SW[7]&~SW[6]&~SW[5]&SW[4]);
   assign HEX4[5]=(~SW[7]&~SW[6]&~SW[5]&SW[4])|(~SW[7]&~SW[6]&SW[5]&~SW[4])|(~SW[7]&~SW[6]&SW[5]&SW[4])|(~SW[7]&SW[6]&SW[5]&SW[4]);
   assign HEX4[6]=(~SW[7]&~SW[6]&~SW[5]&~SW[4])|(~SW[7]&~SW[6]&~SW[5]&SW[4])|(~SW[7]&SW[6]&SW[5]&SW[4]);
   
   /*display B1 = SW[3:0] on HEX4*/
   assign HEX5[0]=(~SW[2]&~SW[1]&SW[0])|(~SW[3]&SW[2]&~SW[1]&~SW[0]);
   assign HEX5[1]=(~SW[3]&SW[2]&~SW[1]&SW[0])|(~SW[3]&SW[2]&SW[1]&~SW[0]);
   assign HEX5[2]=(~SW[3]&~SW[2]&SW[1]&~SW[0]);
   assign HEX5[3]=(~SW[3]&~SW[2]&~SW[1]&SW[0])|(SW[2]&~SW[1]&~SW[0])|(SW[2]&SW[1]&SW[0]);
   assign HEX5[4]=(~SW[3]&~SW[2]&~SW[1]&SW[0])|(~SW[3]&~SW[2]&SW[1]&SW[0])|(~SW[3]&SW[2]&~SW[1]&~SW[0])|(~SW[3]&SW[2]&~SW[1]&SW[0])|
                  (~SW[3]&SW[2]&SW[1]&SW[0])|(SW[3]&~SW[2]&~SW[1]&SW[0]);
   assign HEX5[5]=(~SW[3]&~SW[2]&~SW[1]&SW[0])|(~SW[3]&~SW[2]&SW[1]&~SW[0])|(~SW[3]&~SW[2]&SW[1]&SW[0])|(~SW[3]&SW[2]&SW[1]&SW[0]);
   assign HEX5[6]=(~SW[3]&~SW[2]&~SW[1]&~SW[0])|(~SW[3]&~SW[2]&~SW[1]&SW[0])|(~SW[3]&SW[2]&SW[1]&SW[0]);

   // BCD Adder
   always @(/*AS*/A0 or A1 or B0 or B1)begin
      {cy, x0} = A0 + B0;
      bcd_cy = cy | x0[3]&(x0[2] | x0[1]);
      S0 = (bcd_cy) ? x0+6 : x0;
      {cy, x1} = A1 + B1 + bcd_cy;
      S2[0] = cy | x1[3]&(x1[2] | x1[1]);
      S1 = (S2[0]) ? x1 + 6 : x1;
      S2[3:1] = 0;
   end

   // DISPLAY BCD SUM
   always @(/*AS*/S0 or S1 or S2)begin
      // Display S0
      case (S0[3:0])
        4'b0000: begin
           HEX0[0] = 0;
           HEX0[1] = 0;
           HEX0[2] = 0;
           HEX0[3] = 0;
           HEX0[4] = 0;
           HEX0[5] = 0;
           HEX0[6] = 1;
        end
        4'b0001: begin
           HEX0[0] = 1;
           HEX0[1] = 0;
           HEX0[2] = 0;
           HEX0[3] = 1;
           HEX0[4] = 1;
           HEX0[5] = 1;
           HEX0[6] = 1;
           end
        4'b0010: begin
           HEX0[0] = 0;
           HEX0[1] = 0;
           HEX0[2] = 1;
           HEX0[3] = 0;
           HEX0[4] = 0;
           HEX0[5] = 1;
           HEX0[6] = 0;
        end
        4'b0011: begin
           HEX0[0] = 0;
           HEX0[1] = 0;
           HEX0[2] = 0;
           HEX0[3] = 0;
           HEX0[4] = 1;
           HEX0[5] = 1;
           HEX0[6] = 0;
        end
        4'b0100: begin
           HEX0[0] = 1;
           HEX0[1] = 0;
           HEX0[2] = 0;
           HEX0[3] = 1;
           HEX0[4] = 1;
           HEX0[5] = 0;
           HEX0[6] = 0;
        end
        4'b0101: begin
           HEX0[0] = 1;
           HEX0[1] = 0;
           HEX0[2] = 0;
           HEX0[3] = 0;
           HEX0[4] = 1;
           HEX0[5] = 0;
           HEX0[6] = 0;
        end
        4'b0110: begin
           HEX0[0] = 0;
           HEX0[1] = 1;
           HEX0[2] = 0;
           HEX0[3] = 0;
           HEX0[4] = 0;
           HEX0[5] = 0;
           HEX0[6] = 0;
        end
        4'b0111: begin
           HEX0[0] = 1;
           HEX0[1] = 1;
           HEX0[2] = 1;
           HEX0[3] = 1;
           HEX0[4] = 0;
           HEX0[5] = 0;
           HEX0[6] = 0;
        end
        4'b1000: begin
           HEX0[0] = 0;
           HEX0[1] = 0;
           HEX0[2] = 0;
           HEX0[3] = 0;
           HEX0[4] = 0;
           HEX0[5] = 0;
           HEX0[6] = 0;
        end
        4'b1001: begin
           HEX0[0] = 0;
           HEX0[1] = 0;
           HEX0[2] = 0;
           HEX0[3] = 0;
           HEX0[4] = 1;
           HEX0[5] = 0;
           HEX0[6] = 0;
        end
        default : begin
           HEX0[0] = 1;
           HEX0[1] = 1;
           HEX0[2] = 1;
           HEX0[3] = 1;
           HEX0[4] = 1;
           HEX0[5] = 1;
           HEX0[6] = 1;
        end
      endcase

      // Display S1
      case (S1[3:0])
        4'b0000: begin
           HEX1[0] = 0;
           HEX1[1] = 0;
           HEX1[2] = 0;
           HEX1[3] = 0;
           HEX1[4] = 0;
           HEX1[5] = 0;
           HEX1[6] = 1;
        end
        4'b0001: begin
           HEX1[0] = 1;
           HEX1[1] = 0;
           HEX1[2] = 0;
           HEX1[3] = 1;
           HEX1[4] = 1;
           HEX1[5] = 1;
           HEX1[6] = 1;
        end
        4'b0010: begin
           HEX1[0] = 0;
           HEX1[1] = 0;
           HEX1[2] = 1;
           HEX1[3] = 0;
           HEX1[4] = 0;
           HEX1[5] = 1;
           HEX1[6] = 0;
        end
        4'b0011: begin
           HEX1[0] = 0;
           HEX1[1] = 0;
           HEX1[2] = 0;
           HEX1[3] = 0;
           HEX1[4] = 1;
           HEX1[5] = 1;
           HEX1[6] = 0;
        end
        4'b0100: begin
           HEX1[0] = 1;
           HEX1[1] = 0;
           HEX1[2] = 0;
           HEX1[3] = 1;
           HEX1[4] = 1;
           HEX1[5] = 0;
           HEX1[6] = 0;
        end
        4'b0101: begin
           HEX1[0] = 1;
           HEX1[1] = 0;
           HEX1[2] = 0;
           HEX1[3] = 0;
           HEX1[4] = 1;
           HEX1[5] = 0;
           HEX1[6] = 0;
        end
        4'b0110: begin
           HEX1[0] = 0;
           HEX1[1] = 1;
           HEX1[2] = 0;
           HEX1[3] = 0;
           HEX1[4] = 0;
           HEX1[5] = 0;
           HEX1[6] = 0;
        end
        4'b0111: begin
           HEX1[0] = 1;
           HEX1[1] = 1;
           HEX1[2] = 1;
           HEX1[3] = 1;
           HEX1[4] = 0;
           HEX1[5] = 0;
           HEX1[6] = 0;
        end
        4'b1000: begin
           HEX1[0] = 0;
           HEX1[1] = 0;
           HEX1[2] = 0;
           HEX1[3] = 0;
           HEX1[4] = 0;
           HEX1[5] = 0;
           HEX1[6] = 0;
        end
        4'b1001: begin
           HEX1[0] = 0;
           HEX1[1] = 0;
           HEX1[2] = 0;
           HEX1[3] = 0;
           HEX1[4] = 1;
           HEX1[5] = 0;
           HEX1[6] = 0;
        end
        default : begin
           HEX1[0] = 1;
           HEX1[1] = 1;
           HEX1[2] = 1;
           HEX1[3] = 1;
           HEX1[4] = 1;
           HEX1[5] = 1;
           HEX1[6] = 1;
        end
      endcase // case (S1[3:0])
      
      // Display S2 S2 can only be 0 or 1
      case (S2[3:0])
        4'b0000: begin
           HEX2[0] = 0;
           HEX2[1] = 0;
           HEX2[2] = 0;
           HEX2[3] = 0;
           HEX2[4] = 0;
           HEX2[5] = 0;
           HEX2[6] = 1;
        end
        4'b0001: begin
           HEX2[0] = 1;
           HEX2[1] = 0;
           HEX2[2] = 0;
           HEX2[3] = 1;
           HEX2[4] = 1;
           HEX2[5] = 1;
           HEX2[6] = 1;
        end
        default : begin
           HEX2[0] = 1;
           HEX2[1] = 1;
           HEX2[2] = 1;
           HEX2[3] = 1;
           HEX2[4] = 1;
           HEX2[5] = 1;
           HEX2[6] = 1;
        end
      endcase // case (S2[3:0])
   end // always @ (...
endmodule // Lab2ex2part5

lynk111 · Jul 10, 2011

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How to fix problem in my Verilog code

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