andrew257
Member level 2
hi all,
i keep getting an error message when i try to compile my verilog code.
it refers to a multi source. Now i can see where the error is occuring but i dont know how to fix it.
basically i have the outputs of 3 modules all connecting to the same input on another module.
e.g
output1 ----------|
output2 ----------|-----------input1
output3 ----------|
is there away around this?
thanks
i keep getting an error message when i try to compile my verilog code.
it refers to a multi source. Now i can see where the error is occuring but i dont know how to fix it.
basically i have the outputs of 3 modules all connecting to the same input on another module.
e.g
output1 ----------|
output2 ----------|-----------input1
output3 ----------|
is there away around this?
thanks