Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

How to fix DRC'S in physical design?

Status
Not open for further replies.
Drc, as design rule check for layout, you need to reroute manually if the tool is able to success.
Manul routing could be done with digital backend tool, or analog layout tool
 

Most of the DRC violation can be fixed automatically by CAD tools as Cadence's encounter for example (using globalDetailRoute).
Remaining violations have to be fixed manually by PD engineer. You should check your design and see if the design have some failures that causes DRC violations (for example - bad power grid, bad placement of instances etc.).
 

Hai ramagandhi,

The above two guys said was right
Make sure the lef u used was exact one...

If it shows on vias then edit in lef dont to use..
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top