minimum density design rule check
we can wave this error at block level, but we need to fix it at chip level.
for min density---------
to fix this kind of error, if its only related to poly.....then you can put dummy poly strips or blocks ( strips preferred as small devices are effected at time of fabrication if a large body is arround them) and connect them to either vdd or vss.
first try to fill all the empty spaces where ever possible, at the same time try to be as much uniform as you can while placing poly strips as this will have a big impact on the yield.
if min density error is related to both diffusion and poly...........then try to place dummy transistors with large lengths ( fingering can be used) and connect to appropriate powersupply. each terminal (s/d/g/b) either to vdd or vss.
if its related to metal layer...........try increasing the width of the power rails first, then of the fast switching signals like clock. if you have some large spaces then put some metal strips there.
why to fix min density errors...............
if any metal layer or poly or diffusion layer is not uniformly distributed in that case at the time of fabrication blank spaces will be present at places where these layers are not present and at time of etching if this blank space is large enough, then some etchant will accumulate at these places and will effect the reliability to a great extent. so we need to fix these errors as well.
to fix max density errors...........
generally will come in picture
1) for higher metals..
reduce the width of the power rails and other signals.
2) in case of memories if you are using rings as the kind of power supplies.............and both horizontal and vertical rings are of the same metal.
in this case you can cahnge the metal slotting option or the spacing between the rings, small change in any of these will have a significant effect.( but again it depens on the macro size and ring widths....for small macro it will be difficult to fix.)