urian
Full Member level 3
hi,there
I am designing a MDAC for pipelined ADC.
The structure of it is plotted as attachment.
My question is how to simulate the closed-loop gain vs phase of this schematic because it is a switched-capacitor circuit and decrete-time applied.Then,how does spectere do with its stb analysis with this circuit type?And I only need to add a cmdmprobe component at the output of op-amp to do the stb analysis without changing anything else?
I am designing a MDAC for pipelined ADC.
The structure of it is plotted as attachment.
My question is how to simulate the closed-loop gain vs phase of this schematic because it is a switched-capacitor circuit and decrete-time applied.Then,how does spectere do with its stb analysis with this circuit type?And I only need to add a cmdmprobe component at the output of op-amp to do the stb analysis without changing anything else?
