Somewhere in your PDK docu (e.g. in the "analog characterization" description of your process) you should find metal-to-metal and metal-to-substrate capacitance values for each metal layer. Together with the calculated area of the route - if necessary including its fringing capacitance - you can estimate its total capacitance.
A simpler method would be analysis by simulation: here, the SPICE (or SPICE-like) algorithm will perform the calculations for you - and much more accurate. The usual method is to inject a unit (1V) ac voltage at the concerned node and run an ac analysis. The i(f) (of this node) plot will reveal you its total capacitance: C = (1/ω)*(i/v) = (1/2πf)*i (for v=1).
May be you can find its Ctotal directly in the sim data base, if your sim save options allow for it.
Erikl - can you explain your idea in more detail? I am not getting it... In order for SPICE simulations to show the parasitic capacitance of the wires (i.e. interconnects), it needs to be run in post-layout mode - i.e., after performing parasitic capacitance extraction. But, once you ran the parasitic extraction, you know all the parasitic capacitance values - why would you need to run SPICE simulations then?
you're right: all the parasitics are available after extraction. However, a SPICE simulation
1. relieves you from the task of adding several of them, especially if they are distributed over several metal layers - and SPICE won't forget any of them ;-)
2. if such a node is connected to a device terminal, there will probably be voltage-dependent caps adding to Ctotal. SPICE can add those voltage-dependent caps, which might be desirable if you wish its Ctotal in a real application.
On (1) - does not your design environment allow you to see the total capacitance (without having go through a tedious manual addition of all the coupling capacitance components)?
In DSPF (or SPICE netlist) generated by parasitic extraction tools, total net capacitance are reported and can be easily seen directly...
On (2) - running SPICE simulation is an advantage if you'd like to see the total (interconnects and devices) capacitance, but disadvantage if you'd like to see only parasitic capacitance...