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There may be a couple of ways to report number of flops in a design;
1 - Simplest may be to do "grep" on the netlist with specific filtering or regular expression (e.g. reference cell name or pattern)
2 - Writing you tcl/perl script to count it (using regular experssion or giving whole set of register on that technology and checking each line of the verilog)
3 - Using the synthesis, physical design or STA tool's native commands (as stated above "report_all_reg", etc...)