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How to find number of registers in a design?

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Junior Member level 2
Jun 17, 2011
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This is the an interview question. Please help me finding answer for it.

in DC, we can get the no of registers in the design.

we can use command like report_all_reg in DC shell.

It will give the no of registers in the design.

correct me if I am wrong..
Even i dont know the exact answer for it.... lets say we have a netlist... before doing pd.. Can we find number of flops, instances in the design?

If You are given a netlist and you have to find number of FLOPS from i.

Thing is if you know what kind of technology it is and what FF primitives exist in that technology like : FD,FDCE,FD and so on

If you get the list of FLOP primitive names, we can create a perl script to get the count.
If you compile the design in the compilation report we get the number of registers and the gates used in FPGA's.If I am wrong please correct me.
Hi Kirangu,

There may be a couple of ways to report number of flops in a design;

1 - Simplest may be to do "grep" on the netlist with specific filtering or regular expression (e.g. reference cell name or pattern)
2 - Writing you tcl/perl script to count it (using regular experssion or giving whole set of register on that technology and checking each line of the verilog)
3 - Using the synthesis, physical design or STA tool's native commands (as stated above "report_all_reg", etc...)

I hope it helps,
synopsys DC can report num of regs in design

how about [all_registers] and count the number using some script?

If you're taking SOC-Encounter as a tool, You can use the "dbIsCellSequential" command to find out the sequential elements.

Hiii, In DC there is a command "report_clock_gating" with this u can find total no. of registers , clock gated registers nd un gated registers.....

sizeof_coll [all_reg ] ; Will give register count
sizeof_coll [all_reg -edge] ; Will give Flop count
sizeof_coll [all_reg -level] ; Will give Latch count

these commands will work in DC /PT


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