username_123
Newbie level 1
module A ( output A_OPORT_1 ); endmodule
module B ( input B_IPORT_1 ); endmodule
module A_Tb; A A_inst ( .A_OPORT_1 (A_to_B) ); endmodule
module B_Tb; B B_inst ( .B_IPORT_1 (A_to_B) ); endmodule
Here basically, output port A:A_inst:A_OPORT_1 is connected to input port B:B_inst:B_IPORT_1
How can I retrieve all parts of that information using a verilog PLIs? Example appreciated.
module B ( input B_IPORT_1 ); endmodule
module A_Tb; A A_inst ( .A_OPORT_1 (A_to_B) ); endmodule
module B_Tb; B B_inst ( .B_IPORT_1 (A_to_B) ); endmodule
Here basically, output port A:A_inst:A_OPORT_1 is connected to input port B:B_inst:B_IPORT_1
How can I retrieve all parts of that information using a verilog PLIs? Example appreciated.