One input signal whose width maybe less than one CLK,
If that happen, circuit should deal as invaild signal, I think sync. input signal use posedge and negedge CLK will be good idea?
How to implement the approach? also If I would like to filter noise whose width is less than 2 CLK?
Re: How to filter the noise whose width is less than one CLK
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
signal_d1 <= #1 1'b0;
signal_d2 <= #1 1'b0;
end else begin
signal_d1 <= #1 signal_in;
signal_d2 <= #1 signal_d1;
end
end
always @(posedge clk or negedge rst_n) begin
if (~rst_n)
filtered_signal <= #1 1'b0
else if (signal_d1 == signal_d2)
filtered_signal <= #1 signal_d2;
end
above code can eliminate noise with width less than one clock cycle.
packet said:
One input signal whose width maybe less than one CLK,
If that happen, circuit should deal as invaild signal, I think sync. input signal use posedge and negedge CLK will be good idea?
How to implement the approach? also If I would like to filter noise whose width is less than 2 CLK?