Hi,
For write operation : clock enable of write address counter --> ON time= 844.8 usec and OFF time= 145.2 usec
Inclock of RAM and write Address counter--> 3.3 usec
For Read operation : Clock Enable of read address counter --> OFF time= 844.8 usec and ON time= 145.2 usec
( Inversion of Clock Enable of write address counter)
outclock of RAM and read address counter --> 62.5 nsec
within 990 usec, that is 844.8usec + 145.2 usec, i have to write and read the ram.
1) Write portion is clear, within 844.8 usec = 3.3usec * 256 data will be written into the RAM. at every 844.8 usec, 6 RAM gets filled parallely.
2) Regarding the read portion, within 145.2 usec. i have to send all data from the RAM.
So i am using 8x1 multiplexer to switch the RAM. As already discussed, i am using 11 bit counter from which
Q8 to Q10 is fed to the 3-bit select line.
clock of 11 bit counter for Select line --> 62.5 nsec (same as outclock)
clock enable of 11 bit counter --> OFF time= 844.8 usec and ON time= 145.2 usec ( same as Clock Enable of read address counter)
clock enable ON time of 11 bit counter is 145.2 usec.
clock is 62.5 usec.
For 1 ram to be sent out = 62.5 nsec x 256 data = 16 usec
For 8 rams to be sent out(using 8x1 mux) = 16 usec x8 = 128 usec.
1 st ram = 16 usec
2 nd ram = 32 usec
3rd ram = 48 usec
4th ram = 64 usec
5th ram = 80 usec
6th ram = 96 usec
7th ram ( dummy zeros) = 112 usec
8th ram( dummy zeros) = 128 usec
So remaining 145.2usec - 128 = 17.2 usec remains. 11 bit counter clock will run continuously. so that 17.2 usec time the counter state will also get changed. what to be done in this case. only in 128 usec, the select line have to be changed. remaining 17.2 usec , the state should not get changed. how to skip this 17.2 usec?
can you please let me know.?
Thanks,
V. Prakash
https://obrazki.elektroda.pl/9_1323750851.jpg