How to fill a RAM using VHDL code?

[FvM]

There's no output enable in your design, it would need to use an inout port for the signal do. As is, a RAM instance can't be parallel connected which others.

As previously mentioned, FPGA have no internal bi-directional busses or tri-statable drivers. You can use tri-state in a behavioral design description, but it is converted to muxes by the design compiler. Thus using muxed directly is the clearer way to do it. I gave a mux example in post #39.

 

[prakashvenugopal]

Hi,

Yes. As you told, the RAM outputs can not be linked by single wire, I will go for Mux to select the 6 dual port ram with seperate 3.3 usec clock to write the data into the RAM and Seperate 62.5ns clock to read the data from the RAM.

Thanks,
V. Prakash

 

[prakashvenugopal]

Hi,

Please refer the attachment. Can you please tell me how to generate these pulses shown in the attachment.

Thanks,
V. Prakash

 

[FvM]

It's unclear, why you want to use this kind of complex clock pattern. The common method is to supply the RAM clock continuously. You should also consider, that clock gating is at risk to create timing issues in synchronous designs and thus avoided as far as possible. I don't see a purpose for it in this case.

 

[prakashvenugopal]

Hi,

Please refer the attachments. I am going to use dual port ram, one to write the data and other to read the data from the RAM.
1. Refer the attachment of RAM write operation. Within 990 usec, i have to fill that 6 rams and send the filled data out from the Rams. so i am planning to fill the 6 rams in 844.8 usec with clock duration of 3.3usec(inclock) for each clock. that is, 256 data x 3.3usec = 844.8 usec.and

2. Refer the attachment of RAM read operation:
In remaining 145.2 usec, i have to send the data(read the data) with clock duration of 62.5ns(outclock) for each clock, that is 256 data x 62.5 ns= 16 usec for one ram data to be send out. i cannot send all the ram output parallely. so i am using the multiplexer with 3 bit select line. for that mux, select line is fed from the 3 bit address counter. the clock of that 3-bit address counter is 16usec as shown in the timing diagram as mux selection clock. I have to switch the multiplexer for every 16usec using the clock to increment the 3-bit address counter for select line. so, 16usec x 6 ram data = 96 usec. so i am able to send that all 6 ram data within 96usec with the outclock of 62.5ns.

This is my idea to fill and send the 6 ram data within 990 usec. As you told, how i can use the continuous ram clock pulse to fill and send the data.? there is two clock. one is inclock to fill the data and outclock to send the data out.
is there anyother way to achieve this. Please let me know.

Please correct me if i am wrong.


Thanks,
V. Prakash



https://obrazki.elektroda.pl/6_1322728846.jpg

 

[prakashvenugopal]

Hi,

Please refer the attachments. I am going to use dual port ram, one to write the data and other to read the data from the RAM.
1. Refer the attachment of RAM write operation. Within 990 usec, i have to fill that 6 rams and send the filled data out from the Rams. so i am planning to fill the 6 rams in 844.8 usec with clock duration of 3.3usec(inclock) for each clock. that is, 256 data x 3.3usec = 844.8 usec.and

2. Refer the attachment of RAM read operation:
In remaining 145.2 usec, i have to send the data(read the data) with clock duration of 62.5ns(outclock) for each clock, that is 256 data x 62.5 ns= 16 usec for one ram data to be send out. i cannot send all the ram output parallely. so i am using the multiplexer with 3 bit select line. for that mux, select line is fed from the 3 bit address counter. the clock of that 3-bit address counter is 16usec as shown in the timing diagram as mux selection clock. I have to switch the multiplexer for every 16usec using the clock to increment the 3-bit address counter for select line. so, 16usec x 6 ram data = 96 usec. so i am able to send that all 6 ram data within 96usec with the outclock of 62.5ns.

This is my idea to fill and send the 6 ram data within 990 usec. As you told, how i can use the continuous ram clock pulse to fill and send the data.? there is two clock. one is inclock to fill the data and outclock to send the data out.
is there anyother way to achieve this. Please let me know.

Please correct me if i am wrong.


Thanks,
V. Prakash



https://obrazki.elektroda.pl/6_1322728846.jpg

View attachment RAM_Clock_Pulse_Generation_Write_operation.docView attachment RAM_Clock_Pulse_generation_Read_operation.doc

 

[TrickyDicky]

why do you have such strange clock diagrams? the clocks should be running all the time, and write/read enables used to get new data from the memory. You dont even need read enables, you can just hold the address.

Having odd clocks like this is going to cause you problems

 

[prakashvenugopal]

Hi,

I have to fill the ram and send the same 1536 datas from the 6 ram within 990 usec. I am using Inclock to fill the ram and outclock to read the ram. Inclock as 3.3usec and outclock as 62.5ns.
//***************************************
ENTITY ram_simple IS
port ( clk_in : in std_logic;
clk_out : in std_logic;
we : in std_logic;
addr_in : in std_logic_vector( 7 downto 0);
addr_out : in std_logic_vector( 7 downto 0);
data_in : in std_logic_vector( 7 downto 0);
data_out : out std_logic_vector( 7 downto 0)
);
END ram_simple;


ARCHITECTURE fe2 OF ram_simple IS

TYPE mem_type IS ARRAY ( 255 DOWNTO 0) OF std_logic_vector (7 DOWNTO 0);
SIGNAL mem : mem_type;
--SIGNAL address_int : unsigned(7 DOWNTO 0);

BEGIN -- ex2

l0 : PROCESS (clk_in,clk_out,we,addr_in,addr_out)

begin
if clk_in'event and clk_in = '1' then
if (we = '1') then
mem( conv_integer( addr_in)) <= data_in ;
end if ;
end if ;

if clk_out'event and clk_out = '1' then
data_out <= mem( conv_integer( addr_out)) ;
end if ;
end process;

END fe2;
*********************************

write condition: while inclock is given with we =1, the data is written into the ram, (no outclock)
read condition: while outclock is given, the data is read from the ram.(no inclock)

if i give both inclock and outclock continuously, it will send the data out immediately know?
How to do this.? anyhow i have to stop outclock when write operation and have to stop inclock when read operation.
How to give the clock continously with the above code?
Please let me know.

Thanks,
V. Prakash

 

[TrickyDicky]

How to do this.? anyhow i have to stop outclock when write operation and have to stop inclock when read operation.

No you dont. The data will only be written to the ram when we = '1', so it doesnt matter if the clock keeps running - this is how memories usually work.
Also with the read clock - its down to the read address changing when the data changes. So you just hold the read address until you have the data you want.

You should run the inclock and outclock all the time, at the same time.

 

[prakashvenugopal]

Hi,

I am planning to use 8 bit counter for address bus(7:0) . Two seperate 8 bit counter, one for write address and one for read address.

Inclock of RAM and 8 bit counter clock of write address is same
In the same way, outclock of RAM and 8 bit counter clock of read address is same.

while write operation, inclock and 8 bit counter clock of write address will be like this

1st inclock of ram = 1st 8 bit counter clock= address 00000001 = data1
2nd inclock of ram = 2nd 8 bit counter clock= address 00000010 = data2
3rd inclock of ram = 3rd 8 bit counter clock= address 00000011 = data3
"
"
"
256th inclock of ram = 256th 8 bit counter clock = address 1111 1111 = data256

while read operation, outclock and 8 bit counter clock of read address:

outclock of RAM and 8 bit counter clock of read address is same.
if i give outclock continously the read address counter will also gets running as the clock of ram and read address counter is same.
How to hold the read address? in that read address case, we have to stop the 8 bit counter clock? otherwise anyother way to feed the address
without using 8 bit counter. please tell me know.

Thanks,
V. Prakash

 

[FvM]

You stop the counter by deasserting a clock enable, not by stopping the clock. That's how synchronous design works.

For a counter with clock enable, you can write something like:

if rising_edge(clk) then
  if (enable) then
    count <= count + 1;
  end if;
end if;

May be you find code examples where people did it the other way (gating the clock). But the code was probably written by beginners who didn't yet understand synchronous design principles. The code can synthesize and even work due to the capabilities of design compilers. But it's likely to fail in timing analysis. That's why we harp on about using continuous clocks.

 

[prakashvenugopal]

Hi,

I will give the inclock and outclock continuously to the RAM and 8 bit address counter clock as you suggest.

In the write operation condition:
1) continuous clock to the RAM(Inclock)
2) write enable = 1
3) continuous 8 bit address counter clock same as ram clock
4) clock Enable =1 to run the 8 bit counter 0000 0000 to 1111 1111

In the read operation condition:
1) continuous clock to the RAM(Outclock)
2) write enable = 0
3) continuous 8 bit address counter clock same as ram clock
4) Enable =1 to run the 8 bit counter 0000 0000 to 1111 1111

Yes. In the read case, we can hold the read address by deasserting the clock enable. that time when the outclock is running. It will
send the data of read address 0000 0000 to the data_out port know. whenever the outclock is running, even the clock enable of 8-bit address counter of read operation is disable, the holded address(assume the counter state as 0000 0000) data will be sent to data_out port know.
what i have to do is, first have to fill the ram and then only have to sent the data to the data_out. if i give outclock continoulsy, the data corresponding to the address will be sent out continuously. correct? please correct me if i am wrong.


Thanks,
V. Prakash


https://obrazki.elektroda.pl/12_1323063840.jpg

 

[FvM]

Sounds basically correct.

 

[prakashvenugopal]

Hi,

In the read case, how to handle this. during write operation, when the outclock is running, even though the read address counter clock enable is low which points to address 0000 0000, the data will be sent out to data_out port. Even when the outclock is running, the data should not go out from the data_out. how to do this.? I have to fill the ram and then sent that out the ram data. please give some idea on this. ?

Thanks,
V. Prakash

 

[FvM]

I don't understand the problem with RAM data output. As a first step, the RAM data goes to a multiplexer. If you want constant or zero output from the multiplexer, provide a seventh multiplexer channel with constant input.

Generally, a digital data channel can't send no data. At best it can send constant data.

 

[prakashvenugopal]

Hi,

Now i am clear about ram accessing and the address counter access with clockenable. Now i have to synchronize the RAM with the Multiplexer.

RAM inclock = 3.3 usec
RAM outclock = 62.5 nsec
These two inclock and outclock are same for 6 RAMS


within 990 usec, i have to fill all these 6 RAMS and send all 1536 data out one by one.
For 256 datas write => 3.3usec x 256 data = 844.8usec
parallely 6 rams are filled within 844.8 usec
So, remaining 990 usec - 844.8 usec = 144.2 usec

Within 144.2usec, i have to send these 6 RAM datas( 1536 datas out) synchronizing the multiplexer.
Since ram output cannot be linked, i have to go for multiplexer only and i have to synchronize the multiplexer with
the ram.

I am planning to use the 3-bit counter for multiplexer select line.
For select line = 000 = RAM 1 data should go out
For select line = 001 = RAM 2 data should go out
For select line = 010 = RAM 3 data should go out
For select line = 011 = RAM 4 data should go out
For select line = 100 = RAM 5 data should go out
For select line = 101 = RAM 6 data should go out
For select line = 110 = constant data =0000 0000
For select line = 111 = constant data =0000 0000

I am planning to use 62.5 nsec clock for outclock.
for 1st ram read = 62.5 ns x256 data = 16 usec .
for 6 rams to be read = 62.5nsec x256x6 = 96 usec.

Can you please suggest me how to synchronize these 6 RAMs with the multiplexer to send these 1536 datas
in the sequence within this 144.2 usec timing. Please let me know.

Thanks,
V. Prakash

 

[TrickyDicky]

use the outclock for the multiplexor.

 

[prakashvenugopal]

Hi,

Multiplexer doesnt had a clock. You are telling about 3-bit counter clock for select line? (will be same as outclock)

if i give this 62.5nsec clock to 3-bit counter clock, for each clock the select line will change as follows:
For select line = 000 = for 1st clock
For select line = 001 = for 2nd clock
For select line = 010 = for 3rd clock
For select line = 011 = for 4th clock
For select line = 100 = for 5th clock
For select line = 101 = for 6th clock
For select line = 110 = for 7th clock
For select line = 111 = for 8th clock

I have to send the 1536 datas in the order of ram 1,2,3,4,5 and 6.
For 1 ram datas to be send out will need 256x62.5ns = 16usec.
If i give 62.5nsec clock to the 3-bit counter clock of select line , it will switch the ram for each 62.5nsec know.
How to solve this? please let me know.

thanks,
V. Prakash

 

[TrickyDicky]

ok, no clock on the multiplexor.

But for the counter, just make it 11 bits and use the MSB 3 bits for the multiplexor. The address will only change every 256 clocks then

 

[FvM]

The address will only change every 256 clocks then

There are both options, interleaved and blockwise readout. Apparently, interleaved readout has been assumed so far. It's mainly a question of intended data order for further processing. The interface speed is the same in both cases, RAM clock speed of 16 MHz is a low number for recent FPGAs anyway.