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How to do this.? anyhow i have to stop outclock when write operation and have to stop inclock when read operation.
if rising_edge(clk) then
if (enable) then
count <= count + 1;
end if;
end if;
There are both options, interleaved and blockwise readout. Apparently, interleaved readout has been assumed so far. It's mainly a question of intended data order for further processing. The interface speed is the same in both cases, RAM clock speed of 16 MHz is a low number for recent FPGAs anyway.The address will only change every 256 clocks then
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