How to fill a RAM using VHDL code?

[prakashvenugopal]

Hi,

But for the counter, just make it 11 bits and use the MSB 3 bits for the multiplexor. The address will only change every 256 clocks then

Thanks. Can you please explain this in details. I am not clear in the above mentioned point. 8x1 multiplexer will have the 3-bit select line
3-bit select line is fed from the 3-bit counter(Q0 to Q2). For every clock of 3-bit counter (same as outclock) = 62.5nsec, the select line will
get changed. the select line have to be changed from 000 to 001 after 256 datax62.5nsec = 16 usec only. Can you please explain the above point in detail. Please let me know.

Thanks,
V. Prakash

 

[TrickyDicky]

you make the counter 11 bits:

signal count : unsigned(10 downto 0);

clock it with the outclock:

cnt_proc : process(outclk)
begin
  if rising_edge(outclk) then
    count <= count + 1;
  end if;
end process;

and then connect the 3 MSBs to the mux:

mux_sel <= count(10 downto 8);

this way mux sel only changes every 256 clocks.

 

[prakashvenugopal]

Hi,

For write operation : clock enable of write address counter --> ON time= 844.8 usec and OFF time= 145.2 usec
Inclock of RAM and write Address counter--> 3.3 usec

For Read operation : Clock Enable of read address counter --> OFF time= 844.8 usec and ON time= 145.2 usec
( Inversion of Clock Enable of write address counter)
outclock of RAM and read address counter --> 62.5 nsec

within 990 usec, that is 844.8usec + 145.2 usec, i have to write and read the ram.

1) Write portion is clear, within 844.8 usec = 3.3usec * 256 data will be written into the RAM. at every 844.8 usec, 6 RAM gets filled parallely.

2) Regarding the read portion, within 145.2 usec. i have to send all data from the RAM.
So i am using 8x1 multiplexer to switch the RAM. As already discussed, i am using 11 bit counter from which
Q8 to Q10 is fed to the 3-bit select line.
clock of 11 bit counter for Select line --> 62.5 nsec (same as outclock)
clock enable of 11 bit counter --> OFF time= 844.8 usec and ON time= 145.2 usec ( same as Clock Enable of read address counter)



clock enable ON time of 11 bit counter is 145.2 usec.
clock is 62.5 usec.
For 1 ram to be sent out = 62.5 nsec x 256 data = 16 usec
For 8 rams to be sent out(using 8x1 mux) = 16 usec x8 = 128 usec.

1 st ram = 16 usec
2 nd ram = 32 usec
3rd ram = 48 usec
4th ram = 64 usec
5th ram = 80 usec
6th ram = 96 usec
7th ram ( dummy zeros) = 112 usec
8th ram( dummy zeros) = 128 usec


So remaining 145.2usec - 128 = 17.2 usec remains. 11 bit counter clock will run continuously. so that 17.2 usec time the counter state will also get changed. what to be done in this case. only in 128 usec, the select line have to be changed. remaining 17.2 usec , the state should not get changed. how to skip this 17.2 usec?
can you please let me know.?

Thanks,
V. Prakash


https://obrazki.elektroda.pl/9_1323750851.jpg

 

[prakashvenugopal]

Hi,

For write operation : clock enable of write address counter --> ON time= 844.8 usec and OFF time= 145.2 usec
Inclock of RAM and write Address counter--> 3.3 usec

For Read operation : Clock Enable of read address counter --> OFF time= 844.8 usec and ON time= 145.2 usec
( Inversion of Clock Enable of write address counter)
outclock of RAM and read address counter --> 62.5 nsec

within 990 usec, that is 844.8usec + 145.2 usec, i have to write and read the ram.

1) Write portion is clear, within 844.8 usec = 3.3usec * 256 data will be written into the RAM. at every 844.8 usec, 6 RAM gets filled parallely.

2) Regarding the read portion, within 145.2 usec. i have to send all data from the RAM.
So i am using 8x1 multiplexer to switch the RAM. As already discussed, i am using 11 bit counter from which
Q8 to Q10 is fed to the 3-bit select line.
clock of 11 bit counter for Select line --> 62.5 nsec (same as outclock)
clock enable of 11 bit counter --> OFF time= 844.8 usec and ON time= 145.2 usec ( same as Clock Enable of read address counter)



clock enable ON time of 11 bit counter is 145.2 usec.
clock is 62.5 usec.
For 1 ram to be sent out = 62.5 nsec x 256 data = 16 usec
For 8 rams to be sent out(using 8x1 mux) = 16 usec x8 = 128 usec.

1 st ram = 16 usec
2 nd ram = 32 usec
3rd ram = 48 usec
4th ram = 64 usec
5th ram = 80 usec
6th ram = 96 usec
7th ram ( dummy zeros) = 112 usec
8th ram( dummy zeros) = 128 usec


So remaining 145.2usec - 128 = 17.2 usec remains. 11 bit counter clock will run continuously. so that 17.2 usec time the counter state will also get changed. what to be done in this case. only in 128 usec, the select line have to be changed. remaining 17.2 usec , the state should not get changed. how to skip this 17.2 usec?
can you please let me know.?

Thanks,
V. Prakash


https://obrazki.elektroda.pl/9_1323750851.jpg

 

[TrickyDicky]

why not use a simulator and find out?

 

[prakashvenugopal]

Hi,

Yes. we can do that. but in schematic level analysis itself we had the remaining time of 17.2 usec in the read operation.

As i mentioned earlier:
clock enable ON time of 11 bit counter is 145.2 usec.
clock is 62.5 usec.
For 1 ram to be sent out = 62.5 nsec x 256 data = 16 usec
For 8 rams to be sent out(using 8x1 mux) = 16 usec x8 = 128 usec.

1 st ram = 16 usec
2 nd ram = 32 usec
3rd ram = 48 usec
4th ram = 64 usec
5th ram = 80 usec
6th ram = 96 usec
7th ram ( dummy zeros) = 112 usec
8th ram( dummy zeros) = 128 usec


So remaining 145.2usec - 128 = 17.2 usec remains by shematic level. By schematic level analysis itself we had a query on this.?

Is there any other way to do this by adjusting the inclock and outclock. my requirement
is to write and read the datas within 990 usec. no matter about the adjusting the frequency of inclock and outclock. my intention is to do the process within 990usec.
Can you please give some idea on this?

Thanks,
V. Prakash

 

[TrickyDicky]

turn the clock enable off earlier?

 

[prakashvenugopal]

Hi,

a) Before --> clock enable ON time of 11 bit counter is 145.2 usec. (same as clock enable for read counter)

b) Proposed -->1) clock enable ON time of 11 bit counter is 128 usec. (145.2 - 17.2 = 128 usec) (17.2 usec is skipped)
2) clock enable for read counter is 145.2 usec. ?

am i right.? Please correct me if i am wrong.

Thanks,
V. Prakash

 

[TrickyDicky]

You should really be doing all this debugging yourself.

 

[prakashvenugopal]

Hi,

Thanks. I will try to do these debugging.

thanks,
V. Prakash