signal addr: integer range 0 to 255;
if rising_edge(clk) then
if do_init = '1' then
ram(addr) <= std_logic_vector(to_unsigned(addr,8));
if addr <255 then
addr <= addr + 1;
else
do_init <= '0';
end if;
end if;
end if;
External inputs are clock and Din[7:0] only and Write Enable[we] is pulled up always to write to RAM.The output is Dout[7:0]. How to change this above code as my address is not a external address.? How to do this.
We use cookies and similar technologies for the following purposes:
Do you accept cookies and these technologies?
We use cookies and similar technologies for the following purposes:
Do you accept cookies and these technologies?