How to fill a 2D array in VHDL

[a_fetoh]

hello,
how can i insert data into a 2D array element by element.
I tried this code


process(datain,clk)
begin
for j in 0 to 6 loop
for i in 0 to 3 loop
array2d(i)(j) <= datain;
end loop;
end loop;

but all elements are filled with the data in in one clock
i want the array takes a 28 clock to be filled with the data in.
how can i do this ?

 

[alexadmin]

hello,
how can i insert data into a 2D array element by element.
I tried this code


process(datain,clk)
for j in 0 to 6 loop
for i in 0 to 3 loop
array2d <= datain;
end loop;
end loop;

but all elements are filled with the data in in one clock
i want the array takes a 28 clock to be filled with the data in.
how can i do this ?

It depends on declarations of array2d and datain as well as detailed operational algorithm. Try following constructions

signal cnt:integer range 0 to 31:=0;
...

process(clk)
begin
if rising_edge(clk) then
   if cnt=27 then
      cnt<=0;
   else
      cnt<=cnt+1;
   end if
   array2d(i) <= datain;
end if;
end process;

 

[a_fetoh]

signal cnt:integer range 0 to 31:=0;
...

process(clk)
begin
if rising_edge(clk) then
if cnt=27 then
cnt<=0;
else
cnt<=cnt+1;
end if
array2d(i) <= datain;
end if;
end process;


but this is vector not array

i've forget something in the code

process(datain,clk)
begin
for j in 0 to 6 loop
for i in 0 to 3 loop
array2d (i)(j) <= datain;
end loop;
end loop

 

[alexadmin]

signal cnt:integer range 0 to 31:=0;

but this is vector not array

i've forget something in the code

process(datain,clk)
begin
for j in 0 to 6 loop
for i in 0 to 3 loop
array2d (i)(j) <= datain;
end loop;
end loop

Ok, the true code is

process(clk) 
begin 
if rising_edge(clk) then 
   if cnt=27 then 
      cnt<=0; 
   else 
      cnt<=cnt+1; 
   end if 
   array2d(integer(cnt/7))(cnt mod 7) <= datain; 
end if; 
end process;

integer() is conversation to integer type and mod is division by modulo 7.
I may make mistakes in syntax.

 

[a_fetoh]

Error:Operator <DIVIDE> must have constant operands or first operand must be power of 2

 

[alexadmin]

Error:Operator <DIVIDE> must have constant operands or first operand must be power of 2

It is very strange. Integer number must be divided without restrictions. What simulation tool is used?

Other decision is to create two integer counters. The first is in range 0 to 3 and the second is in the range 0 to 6. The first counter must be incremented when the second pass over all range.

 

[a_fetoh]

Thanks
I've solved it with your idea

signal  i  : integer range 0 to 17 :=0;
signal  j  : integer range 0 to 31 :=31 ;

begin

process(clk)
begin
	if rising_edge(clk) then
		if i = 17 then
			i <= 0 ;
		else
			i <= i +1 ;
		end if;
	end if;
end process;


process(clk,i)
begin
	if rising_edge(clk) then
			if ( i = 17 and j > 0 ) then
				j <= j - 1 ;
				else
					if (i=17 and j=0) then
			j <= 31;

			end if ;
		end if;
	end if;
end process;


process(clk,i,j)
begin

if rising_edge(clk) then

interleaver(i)(j) <= din;
end if;		

end process;