how to extract multi cycle path

[Amr El Dieb]

I am working on a design that uses some cores from Designware. I took the generated .v netlist from the designware and start putting it in my top level and start the implementation on FPGA.

I am using Xilinx ISE 7.1 to do the implementation, the design is working fine but i want to increase the performance of it, so i just want to ask if there is any way to extract the multi cycle paths in the design in the Xilinx ISE tools as long as i don't have the RTL code???

Thanks