entity two_counters is
port (
clk : in std_logic;
Led0, Led1, Led2, Led3, -- Counter1
Led4, Led5, Led6, Led7 : out std_logic -- Counter2
);
end two_counters;
architecture behavioral of two_counters is
signal cnt1 : std_logic_vector(3 downto 0);
signal cnt2 : std_logic_vector(3 downto 0);
begin
counter1: process(clk)
begin
if raising_edge(clk) then
cnt1 <= cnt1 + 1;
end if;
end process;
counter2: process(clk)
begin
if raising_edge(clk) then
cnt2 <= cnt2 + 1;
end if;
end process;
-- display counter1
Led0 <= cnt1(0);
Led1 <= cnt1(1);
Led2 <= cnt1(2);
Led3 <= cnt1(3);
-- display counter2
Led4 <= cnt2(0);
Led5 <= cnt2(1);
Led6 <= cnt2(2);
Led7 <= cnt2(3);
end behavioral;