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Junior Member level 2
rtl compiler hold time fixing
Hi, can anyone tell me how to estimate the setup and hold time for a given frequency during synthesis. How I account the setup and hold time listed in the synthesis library into my estimation.
When you design a part of a chip, do you receive the requirments of setup and hold time. That is to say that the setup and hold time for that part are fixed before you design the part.
Hi, can anyone tell me how to estimate the setup and hold time for a given frequency during synthesis. How I account the setup and hold time listed in the synthesis library into my estimation.
When you design a part of a chip, do you receive the requirments of setup and hold time. That is to say that the setup and hold time for that part are fixed before you design the part.