How to estimate the setup and hold time for given frequency?

[hover]

rtl compiler hold time fixing

Hi, can anyone tell me how to estimate the setup and hold time for a given frequency during synthesis. How I account the setup and hold time listed in the synthesis library into my estimation.

When you design a part of a chip, do you receive the requirments of setup and hold time. That is to say that the setup and hold time for that part are fixed before you design the part.

 

[zysmith]

rtl compiler hold time

you already knew that setup and hold time listed in standard cell document, why you estimate them.

 

[silencer3]

setup and hold time

pls search topics for SETUP and HOLD times. There are excellent discussions happened on the same. pls do not waste the resources. pls search the forumj and u will get ezxcellent material

 

[visualart]

setup and hold time

check your technoly library, you will find the process requisite the setup time and hold time

 

[amaccormack]

Re: setup and hold time

If you are USING a synthesis tool, then you simply tell it your clock uncertainty and the setup and hold requirements at the I/O of the top level of your block. The synthesis tool will do all the internal analysis required. However, in modern processes there isn't much point estimating hold times until the final layout is done, as clock trees and rotuing make such a big difference. Cadence RTL compiler does not do hold time fixing for this reason.

If you are WRITING a synthesis tool, then you've got an awful lot of learning to do!