Re: setup and hold time
If you are USING a synthesis tool, then you simply tell it your clock uncertainty and the setup and hold requirements at the I/O of the top level of your block. The synthesis tool will do all the internal analysis required. However, in modern processes there isn't much point estimating hold times until the final layout is done, as clock trees and rotuing make such a big difference. Cadence RTL compiler does not do hold time fixing for this reason.
If you are WRITING a synthesis tool, then you've got an awful lot of learning to do!