how to encrypt IP core used for FPGA?

[FLEXcertifydll]

how fpga code is encrypted

FPGA is base on SRAM, every time power up ,source code down to the FPGA. So how to encrypt IP core used for FPGA? And how design the IP core whit time-limited? Did anyone know it?
THX!
:?: :!: :idea:

 

[xirix]

For IP protection you can use Actel devices (both flash and antifuse).
For time-limit use you must implement a protection method in an extern device. For example at power-down read time from a real time clock, save in a flash device...at power-up read flash...and there are a lot of smart (access protected) flash memories.

 

[FLEXcertifydll]

So I must design a machine-status for writing flash and the right position in the source code? At the power-down the clock data save in a protection regist in flash, and at power-up logic detect the protection regist verify the right of IP core. Right?
THX!

 

[tcn]

Xilinx has encryption enabled devices (Virtex devices). I would suggest going this way. The firmware is encrypted at compile time.

tcn

 

[steshenko]

We use little CPLD with special code check circuit and some part of main circuits - and set protect bit. We have no problem with this decision/ CPLD and FPGA work together

 

[volta]

Xilinx Comes to Rescue

Use Xilinx Virtex-II devices for code protection

 

[ddt694]

"Using Xilinx Virtex-II devices for code protection" is not a good choice. The code can be read out when
configuring from eeprom for fpga.

 

[ch_wen]

"Using Xilinx Virtex-II devices for code protection" is not a good choice. The code can be read out when
configuring from eeprom for fpga.

Did you know the Virtex-II features?

 

[dll_embed]

Re: Can FPGA be encrypted?

virtex-II has a triple DES encryption engine built in. You can program the KEY only by JTAG. And the bitstream is encrypted by the KEY. I guess it should be a tough job to recover the original bitstream after it is encrypted.

The only thing inconvient is that it needs a seperate battery to power this circuit.

 

[wasp]

Re: Can FPGA be encrypted?

One of ways of restriction on time is an addition in the project of the counter,which works during time of the sufficient project for demonstration, and then blocks work.

 

[elektryk]

Re: Can FPGA be encrypted?

Lastly I find out smart trick. It need some research but I this it is possible. There is need to be some kind of eeprom or flash memory inside chip that can be written from inside of chip. Every rewriteable device have some limitation about writing it. How about, every use of device, write some kind of signature (every time diffrent) and veryfy it. If write was wrong the time is out.