Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

How to encrypt HDL design files with ability to synthesize ?

Status
Not open for further replies.

PowerEDA2003

Junior Member level 1
Junior Member level 1
Joined
Feb 6, 2003
Messages
18
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
116
site:edaboard.com encrypt verilog -search results

It is possible to encrypt HDL design files for functional simulation. How I can protrct my design during synthesis? I want to give the customer a file, which is synthesizable but its content is not viewable! How I can do it?

Any help?
 

mariaR

Advanced Member level 4
Full Member level 1
Joined
Feb 28, 2003
Messages
110
Helped
3
Reputation
6
Reaction score
2
Trophy points
1,298
Activity points
697
It's an interesting question ! I've never heard such tool. Anyone know?
 

ejean

Junior Member level 3
Junior Member level 3
Joined
Jun 1, 2001
Messages
27
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
151
DesinWare can produce BLOCK IP in encrypted format. If you want to provide your source code in encrypted format, you can choose pre-compiler base HDL simulator, these software can compile the original HDL code to it's "native-code". Modelsim, VCS, NC-verilog, SpeedSim, etc. can do this job.
 

firendchn

Junior Member level 3
Junior Member level 3
Joined
Sep 11, 2002
Messages
29
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
133
Re: Encrypted Design Files

ejean,
give an example pls!
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top