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How to encrypt HDL design files with ability to synthesize ?

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PowerEDA2003

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site:edaboard.com encrypt verilog -search results

It is possible to encrypt HDL design files for functional simulation. How I can protrct my design during synthesis? I want to give the customer a file, which is synthesizable but its content is not viewable! How I can do it?

Any help?
 

mariaR

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It's an interesting question ! I've never heard such tool. Anyone know?
 

ejean

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DesinWare can produce BLOCK IP in encrypted format. If you want to provide your source code in encrypted format, you can choose pre-compiler base HDL simulator, these software can compile the original HDL code to it's "native-code". Modelsim, VCS, NC-verilog, SpeedSim, etc. can do this job.
 

firendchn

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Re: Encrypted Design Files

ejean,
give an example pls!
 

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