no need to have special care on the layout of this capacitor. Just use the available space after layout the transistors to draw the capacitor. Its value is not critical, since due to corners the spread on its value will be big.
What kind of error. Does not recognize the capacitor, or is due to having different area perimeter in schematic from layout. Use the same values in schematic that you have in layout.
If you are using Cadence layout, use a square M2, then a smaller square of "res_id" and then use the same size "M1" , then extract to check the capacitor. The better way of capacitor design is centroid layout method.