How to draw layout for resistor?

[raghavathej]

Hi,

After using resistors and capacitors in my schematic, i am not able to generate resistor/capacitor layouts.
Will the tool itself generate layout for resistor/capacitor ( as the layout for transistor is generated
automatically by clicking from Extract -> All From Source ) ? Else should i draw those layouts all by myself if so
how to draw layout for resistors and capacitor? I am using Cadence Tools.


Thanks in Advance,
Raghava

 

[erikl]

Will the tool itself generate layout for resistor/capacitor ( as the layout for transistor is generated
automatically by clicking from Extract -> All From Source ) ?

Yes it should. May be the corresponding pcells are missing, or the path to them.

 

[raghavathej]

I mean i am using resistor symbol directly from analogLib...So should tool generate the layout of such a resistor too?...Please Explain

- - - Updated - - -

Yes it should. May be the corresponding pcells are missing, or the path to them.

I mean i am using resistor symbol directly from analogLib...So should tool generate the layout of such a resistor too?...Please Explain

 

[erikl]

I am using resistor symbol directly from analogLib...So should tool generate the layout of such a resistor too?...Please Explain

Same question - same answer. Probably you're using the wrong resistor symbol - Cādence' analogLib resistor doesn't have a layout counterpart, it's just an uncommitted part for SPICE simulation. You need to use the correct one for the resistor you want to see in your layout. See your foundry's resistor symbols - probably in the same lib where you get your transistors from. Passive devices like resistors, capacitors etc. are - like transistors - process/layout specific, so should be available in the process-specific libs. If there are none, you'd have to create the layout by your own.

 

[dick_freebird]

analogLib is for schematic uses, it is not bound to any
foundry technology and many devices netlist with
"lvsIgnore='t'" properties (resistors netlist as short,
capacitors as open, rather than having values).

For things that will actually be on your chip, you should
be using a proper devices library and corresponding
techfile, and then you will have the pCells for all the
"legal" components that foundry will print.

 

[raghavathej]

analogLib is for schematic uses, it is not bound to any
foundry technology and many devices netlist with
"lvsIgnore='t'" properties (resistors netlist as short,
capacitors as open, rather than having values).

For things that will actually be on your chip, you should
be using a proper devices library and corresponding
techfile, and then you will have the pCells for all the
"legal" components that foundry will print.

Thank You so much for your valuable time...
I will try to use your suggestions..