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how to do transistor sizing in cadence spectre

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bharathr87

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transistor sizing

how to do transistor sizing in cadence spectre

L= 40nm
W=150nm
no. f fingers=1
multiplier=1
 

DDavid

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Re: transistor sizing

Please be more specific

In generally you have:
L - length
W - wight
F - fingers
m - number of multiplers
 

bhargava834

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Re: transistor sizing

Hello Bharath

First of all can u tell me what is your circuit???

As i know

In cadence u cant go beyond 50um for W or L.

Anyway L is in the range below 50um.
and if u want W to be greater than 50um u can play with No:eek:f fingers and multipliers.

W=No: of fingers * multipliers

No: of fingers is in um s
multipliers is a constant number

It is nothing but u are going to arrange similar transistors in parallel..


Regards
Bhargav
 

bharathr87

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Re: transistor sizing

jus choose the optimum value for w/l...increasin w increases the current n hence the gain n transconductance....increasin l decreases channel length mod. n hence increases rout....
 

Areky_qin

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transistor sizing

you could use any value of W, L and m factor,
and in fact you could use .scale option in hspice to shink you transitor size, for example, you use a PMOS as W=1000u, L=500u, m=100, at the same time you define .option scale=0.01, so you final Pmos size is w=10000*0.0001=100u, L=500*0.01=50u, m=100.

Added after 2 minutes:

sorry for comfuse,
you define w=10000u, l=500u, m=100
and use .option scale=0.01, then
the fize device size is w=10000*0.01=100u,
L=500*0.01=5u,m=100. good luck.
 

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