Hello,
I need to write a VHDL testbench for simulating an FPGA circuit. In the testbench, I want to make an 8 bit waveform (called TB_COUNT) start counting up from zero at 120 ns, and increment by 1 count every 40 ns.
In the past, I've written something like what follows, where TB_COUNT is defined:
signal TB_COUNT : std_logic_vector (7 downto 0) := "00000000";
TB_COUNT <= "00000000" after 120 ns,
"00000001" after 160 ns,
etc
However, I need TB_COUNT to increment 1000x's, so this brute force approach is impractical. So, how do I perform this task elegantly?