How to do this in the VHDL testbench

[pastro]

Hello,

I need to write a VHDL testbench for simulating an FPGA circuit. In the testbench, I want to make an 8 bit waveform (called TB_COUNT) start counting up from zero at 120 ns, and increment by 1 count every 40 ns.

In the past, I've written something like what follows, where TB_COUNT is defined:
signal TB_COUNT : std_logic_vector (7 downto 0) := "00000000";

TB_COUNT <= "00000000" after 120 ns,
"00000001" after 160 ns,
etc


However, I need TB_COUNT to increment 1000x's, so this brute force approach is impractical. So, how do I perform this task elegantly?

 

[alexan_e]

You can use something like

  process 
    begin
     wait for 120 ns;
     for i in 0 to 1000000 loop  
     -- loop      -- you can also use this without the loop counter
      TB_COUNT <=TB_COUNT+1;
      wait for 40 ns;     
     end loop;
     wait;   
    end process;

Alex