Hi,
I want to do system design and verification of a video decoding system. How can I start from the scratch? Any informations, websites or books recommended? I decide to use SystemVerilog to do this task,how do you think?
I only want to do system simulation. About synthesis, I prefer to use verilog. I've heard VCS 7.0 or Modelsim 6.0 supports systemverilog, is that true?
I only want to do system simulation. About synthesis, I prefer to use verilog. I've heard VCS 7.0 or Modelsim 6.0 supports systemverilog, is that true?
Hi,
I want to do system design and verification of a video decoding system. How can I start from the scratch? Any informations, websites or books recommended? I decide to use SystemVerilog to do this task,how do you think?
Hi,
I want to do system design and verification of a video decoding system. How can I start from the scratch? Any informations, websites or books recommended? I decide to use SystemVerilog to do this task,how do you think?
SystemC is a good choice if u r familiar with C language.
Matlab is too high to do system level design. But if u only wanna verify the algorithms, Matlab is easy.
SystemVerilog is not intendeed to be used for system-level modeling.
SystemC is language for you. You don't need any expensive tools in beggining (Some C++ debugger and waveform viewer are enough).
If you are talking about H.264 decoder:
- start with existing JM reference SW is OK. You need to rearange this (or rewrite in C++ to avoid C/SystemC mixing) to clearly separate functions and do profiling to help you decide about HW/SW partitioning.
- after that you need to decide about interfaces between HW modules, make SystemC wrappers around existing C++ classes (if possible, to simplified maintenance of 2 models) and imoplement those interfaces (use aproximate timing modeling). Notice that C++ model remains golden for your SystemC model all the time and both of them need to be maintained.
- make several iterrations in SystemC until you find arhitecture which satisfied your needs. Develop firmware in parallel (you don't need to choose exactly which embedded processor you will use still, except if you are going with some fancy stuff like Tensilica/Arc)
- when SystemC model is stable you could start with HDL writting. If you have nc-verilog and nc-systemc licenses you could simply replace any module in your SystemC model with Verilog and it will work (SystemC-Verilog co-simulation). Notice that you don't need to have separate b-level test environments what is great benefit. Yor SystemC model remain golden for your SystemC-Verilog co-simulation all the time.
- before go to FPGA prototyping perform gate-level (post-synthesis simulation in your SystemC environment)
- develop appropriate custom FPGA platform