Apr 9, 2010 #1 W woeichee Newbie level 5 Joined Jan 17, 2010 Messages 9 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Location Malaysia Activity points 1,348 in verilog, how to do like q <= d[count:0]? reg [3:0] count; thanks
Apr 10, 2010 #2 shitansh Full Member level 5 Joined Jan 6, 2009 Messages 296 Helped 51 Reputation 100 Reaction score 29 Trophy points 1,308 Location India-Gujarat Activity points 3,017 Re: Verilog reg [3:0] count;; reg [15:0] q; wire [15:0] d; always @ (posedge clk or negedge rst_n) begin if (~rst_n) q <= {16{1'b0}}; else q<= d[count:0]; end HTH,
Re: Verilog reg [3:0] count;; reg [15:0] q; wire [15:0] d; always @ (posedge clk or negedge rst_n) begin if (~rst_n) q <= {16{1'b0}}; else q<= d[count:0]; end HTH,