How to do power estimation using cadence tools ?

[anilineda]

Hi,

I want to do accurate power estimation using cadence tools on a simple design with 8 flipflops and a fulladder involved.

the only cadence tools avaialbe with me is, incisive entreprsise and genus.

i learned to generate power report, but this time i want to keep invovle forward saif, backward saif files (came to know from internet) for exact power report . And above that , is there any commands to convert vcd to saif like that .

expecting help from cadence front end tool users.
i can pose the same question to cadence support, but i think edaboard will resolve instead of wasting in raising in webcase

regards,
Anil

 

[ThisIsNotSam]

create a vcd from the simulation. use read_vcd from within genus. do a report_power after. done.

to get more precise you need a full layout, which you don't have if you are only using genus for implementation.

 

[anilineda]

Hi,

thanks for reply.
i used below command after reading sdc file (rad_sdc)and before doing generic synthesis (syn_generic) in the synthesis script.

read_vcd -start_time 20 -end_time 60 -activity_profile -vcd_scope ./adder.vcd

i done synthesis with vcd file and without vcd file, but there is no single change in the power report.
where i am going wrong.

============================================================
Generated by: Genus(TM) Synthesis Solution GENUS15.20 - 15.20-p004_1
Generated on: Dec 05 2016 05:08:03 pm
Module: top
Technology library: tcbn28hpmbwp35cd3nmulvtff0p99vm40c 120
Operating conditions: ff0p99vm40c (balanced_tree)
Wireload mode: segmented
Area mode: timing library
============================================================

Leakage Dynamic Total
Instance Cells Power(nW) Power(nW) Power(nW)
---------------------------------------------
top 19 532.379 5072.394 5604.773
u7 1 71.537 319.712 391.250
u4 2 53.087 499.410 552.497
u5 2 53.087 499.410 552.497
u6 2 52.121 540.478 592.599
u2 2 50.850 531.394 582.244
u3 2 50.549 558.280 608.829
u1 2 50.510 564.365 614.875
u10 2 49.945 542.083 592.028
u11 2 49.126 541.325 590.451
u8 1 25.798 48.203 74.001
u9 1 25.769 48.763 74.532

BTW, the vcd file is atttached with adder.txt and the actual top verilog file as top.txt.

the testbecnch for generating vcd is here

`timescale 1ns /1ns 
module tb;

reg bypass0;
reg a;
reg b;
reg cin;
reg bypass1;
reg sel;
reg rst;
reg clk_top;
wire out_sum;
wire out_cout;


top dut(bypass0,a,b,cin,bypass1,sel,rst,clk_top,out_sum,out_cout);

initial begin
$dumpfile("adder.vcd");
$dumpvars(0,tb);
rst = 1'b1;
#20 rst =1'b0;
bypass0 = 1'b0;
bypass1 = 1'b1;
sel =1'b1;
a = 0 ; b = 0; cin =0;
#10 a = 0 ; b = 0; cin =1;
#10 a = 0 ; b = 1; cin =0;
#10 a = 0 ; b = 1; cin =1;
#10 a = 1 ; b = 0; cin =0;
#10 a = 1 ; b = 0; cin =1;
#10 a = 1 ; b = 1; cin =0;
#10 a = 1 ; b = 1; cin =1;

#10 a = 0 ; b = 0; cin =1;
#10 a = 0 ; b = 1; cin =0;
#10 a = 0 ; b = 1; cin =1;
#10 a = 1 ; b = 0; cin =0;
#10 sel = 1'b0;
#10 $stop;
end
initial clk_top =0;
always #5 clk_top = ~clk_top;
endmodule

Regards,
Anil

 

[ThisIsNotSam]

after you read the vcd, some stats will show up on the screen. see if all of your signals are being asserted. probably not.

 

[anilineda]

after reading vcd file , the stats looks like

reading vcd ..... 0%
reading vcd ......10 %
....
...
reading vcd .....100 %
sucussedfully read vcd.

something like that is there in log file.
In my previous reply i attached vcd file (top.txt) . Inside it, all signals are there.

 

[ThisIsNotSam]

after reading vcd file , the stats looks like

reading vcd ..... 0%
reading vcd ......10 %
....
...
reading vcd .....100 %
sucussedfully read vcd.

something like that is there in log file.
In my previous reply i attached vcd file (top.txt) . Inside it, all signals are there.

please post the entire log. it mentions how many signals were asserted at some point. that is the part that matters.

 

[anilineda]

sorry for delay.
here u see complete log file

 

[ThisIsNotSam]

sorry for delay.
here u see complete log file

your nets were asserted, that is good. generate a different vcd, with a different testbench scenario. see if power changes.

 

[anilineda]

generate a different vcd, with a different testbench scenario. see if power changes.

i did that by commenting some scenarios and ran for 4 combinatinons etc., no change in power report.

something happening. literally read_vcd has no effect that what i observed.

 

[ThisIsNotSam]

something is wrong with your flow. I can assure you vcd is taken into account by report power.