Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
The EDA Tool Post-Compilation Commands > Write Output Netlists command (Processing menu) is only available after you have compiled a project and you have specified a simulation, timing analysis, or board-level simulation EDA tool. If you use this command after the design source files have changed after compilation, the Quartus II software generates the output netlist files with the data from the last compilation.
Allows you to generate Verilog Output Files (.vo), VHDL Output Files (.vhd), and Standard Delay Format Output File (.sdo) for a design. You can compile a design and then specify different EDA tool settings and regenerate the netlist files without recompiling the design. You can also use this command to generate Stamp model files, PartMiner XML-Format Files (.xml), and IBIS Output Files (.ibs).
these's a option in quartusII, "Project--EDA Tools seting", choose ModelSim and then quartusII will generate netlist and sdf files automaticly after compile, either in verilog or vhdl format,(.vo, .sdo, .vho). And then, you should know how to do simulation now, right?