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daskk62
Guest
I want to design a 16-bit up-down counter ASIC. For that firstly I wrote the verilog code for 16-bit up-down counter and synthesized using Cadence genus tool. And Layout is made using cadence Innovus tool. Now I want to check the simulation based result of the layout. How can I check the simulation result of the layout.
For Analog design I did the post layout simulation, where the tool I have used is cadence Virtuoso. And the post layout simulation I obtained after PEX. In digital design how can I do the post layout/netlist simulation.
For Analog design I did the post layout simulation, where the tool I have used is cadence Virtuoso. And the post layout simulation I obtained after PEX. In digital design how can I do the post layout/netlist simulation.