Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

How to do mixed-signal simulation in Cadence SpectreVerilog?

Status
Not open for further replies.

balou3

Newbie level 3
Newbie level 3
Joined
Jul 29, 2003
Messages
3
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
30
mixed-signal simulation

Hello everybody,

I am doing mixed-signal simulation with Cadence SpectreVerilog. I have to apply test vectors to a memory. So, if someone knows: is it possible to use Verilog-XL if arrays are analog and periphery is digital? And, in general, I would like to get more information about mixed-signal simulation with Cadence? :!:
 

Re: mixed-signal simulation

balou3 said:
Hello everybody,

I am doing mixed-signal simulation with Cadence SpectreVerilog. I have to apply test vectors to a memory. So, if someone knows: is it possible to use Verilog-XL if arrays are analog and periphery is digital? And, in general, I would like to get more information about mixed-signal simulation with Cadence? :!:

That's what it call mix-mode simulation. Use Dolphin Smash to solve your problem.
 

Re: mixed-signal simulation

Ok, it could be possible to use Dolphin Smash, but how can I use it together with Cadence. The memory cells are designed by Skill, the periphery by Verilog, or it might be I see the problem in wrong way.[align=left] :?
 

IS THERE ANY GOOK ON THIS SUBJECT?
 

honey said:
IS THERE ANY GOOK ON THIS SUBJECT?

Book, you meant? there are a lot on Amazon, but not free
 

eda and computer books are too expensive.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top