Hi,
I don't think you want to configure the ADRV for LVDS or not.
So please tell us what FPGA you want to configure....And what IDE / Software you use and what language.
Usually FPGAs are internally routed single ended, not LVDS, just the I/O buffers may be configured to translate to LVDS.
There may be several ways to do this, either in your code or in the I/O description files.
There may be restrictions which pins / pin pairs to use, additionally the according bank supply may fit to the desired I/O standard.
Klaus