Re: IO delay in FPGA
for that scale you almost certainly have to move to oversampled outputs. Eg, if an interface sends serial data with a clock, at a rate of 1Mbps, you could provide the module with an 8MHz clock. the output of the module would change only once per 8 cycles. now a variable number of registers can be inserted between the module, and the IO. The number of registers between the modules "serial clock output" and the FPGA's IO pad is intentionally made different than the number between "serial data output" and the FPGA IO pad.